Cfu add enableInit option

This commit is contained in:
Dolu1990 2023-03-22 17:13:47 +01:00
parent 0e59a56bd1
commit 570720fdd8
1 changed files with 3 additions and 2 deletions

View File

@ -104,7 +104,8 @@ class CfuPlugin(val stageCount : Int,
val encodings : List[CfuPluginEncoding] = null, val encodings : List[CfuPluginEncoding] = null,
val stateAndIndexCsrOffset : Int = 0xBC0, val stateAndIndexCsrOffset : Int = 0xBC0,
val statusCsrOffset : Int = 0x801, val statusCsrOffset : Int = 0x801,
val withEnable : Boolean = true) extends Plugin[VexRiscv]{ val withEnable : Boolean = true,
val enableInit : Boolean = false) extends Plugin[VexRiscv]{
def p = busParameter def p = busParameter
assert(p.CFU_INPUTS <= 2) assert(p.CFU_INPUTS <= 2)
@ -176,7 +177,7 @@ class CfuPlugin(val stageCount : Int,
val csr = pipeline plug new Area{ val csr = pipeline plug new Area{
val factory = pipeline.service(classOf[CsrInterface]) val factory = pipeline.service(classOf[CsrInterface])
val en = withEnable generate (Reg(Bool()) init(False)) val en = withEnable generate (Reg(Bool()) init(enableInit))
if(withEnable) factory.rw(stateAndIndexCsrOffset, 31, en) if(withEnable) factory.rw(stateAndIndexCsrOffset, 31, en)
val stateId = Reg(UInt(log2Up(p.CFU_STATE_INDEX_NUM) bits)) init(0) val stateId = Reg(UInt(log2Up(p.CFU_STATE_INDEX_NUM) bits)) init(0)