Privileged debug fake maskmax to 31
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5a8cdee884
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@ -895,6 +895,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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csrrw(CSR.TDATA1, read, 2 -> execute , 3 -> u, 4-> s, 6 -> m, 32 - 5 -> dmode, 12 -> action)
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csrr(CSR.TDATA1, read, 32 - 4 -> tpe)
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csrr(CSR.TDATA1, read, 20 -> B"011111")
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//TODO action sizelo timing select sizehi maskmax
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}
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@ -1631,10 +1632,14 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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}
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}
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// Component.toplevel.rework{
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// out(CombInit(debug.running.pull())).setName("debug0")
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// out(CombInit(pipeline.decode.arbitration.isFiring.pull())).setName("debug1")
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// }
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val csrs = (0x7A0 to 0x7A5)
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val miaouRead = csrs.map(v => isReading(v)).orR
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val miaouWrite = csrs.map(v => isWriting(v)).orR
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Component.toplevel.rework{
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out(CombInit(miaouRead.pull())).setName("debug0")
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out(CombInit(miaouWrite.pull())).setName("debug1")
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}
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}
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}
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}
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