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VexRiscv
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Privileged debug fake maskmax to 31

This commit is contained in:
Dolu1990 2022-11-21 14:01:28 +01:00
parent 5a8cdee884
commit 572ca3fcfa
1 changed files with 9 additions and 4 deletions
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13
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -895,6 +895,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
csrrw(CSR.TDATA1, read, 2 -> execute , 3 -> u, 4-> s, 6 -> m, 32 - 5 -> dmode, 12 -> action) csrrw(CSR.TDATA1, read, 2 -> execute , 3 -> u, 4-> s, 6 -> m, 32 - 5 -> dmode, 12 -> action)
csrr(CSR.TDATA1, read, 32 - 4 -> tpe) csrr(CSR.TDATA1, read, 32 - 4 -> tpe)
csrr(CSR.TDATA1, read, 20 -> B"011111")
//TODO action sizelo timing select sizehi maskmax //TODO action sizelo timing select sizehi maskmax
} }
@ -1631,10 +1632,14 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
} }
} }
// Component.toplevel.rework{ val csrs = (0x7A0 to 0x7A5)
// out(CombInit(debug.running.pull())).setName("debug0") val miaouRead = csrs.map(v => isReading(v)).orR
// out(CombInit(pipeline.decode.arbitration.isFiring.pull())).setName("debug1") val miaouWrite = csrs.map(v => isWriting(v)).orR
// }
Component.toplevel.rework{
out(CombInit(miaouRead.pull())).setName("debug0")
out(CombInit(miaouWrite.pull())).setName("debug1")
}
} }
} }
} }