Fill travis, DhrystoneBench is now a Unit test

This commit is contained in:
Dolu1990 2018-05-28 09:02:01 +02:00
parent 5704f22739
commit 5943ee727e
4 changed files with 49 additions and 152 deletions

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@ -31,22 +31,22 @@ before_install:
- cd ..
# Verilator
#- sudo apt-get install git make autoconf g++ flex bison -y # First time prerequisites
#- git clone http://git.veripool.org/git/verilator # Only first time
#- unset VERILATOR_ROOT # For bash
#- cd verilator
#- git pull # Make sure we're up-to-date
#- git checkout verilator_3_916
#- autoconf # Create ./configure script
#- ./configure
#- make -j$(nproc)
#- sudo make install
#- cd ..
- sudo apt-get install git make autoconf g++ flex bison -y # First time prerequisites
- git clone http://git.veripool.org/git/verilator # Only first time
- unset VERILATOR_ROOT # For bash
- cd verilator
- git pull # Make sure we're up-to-date
- git checkout verilator_3_916
- autoconf # Create ./configure script
- ./configure
- make -j$(nproc)
- sudo make install
- cd ..
- cd VexRiscv
- curl -T README.md -udolu1990:$BINTRAY_KEY https://api.bintray.com/content/spinalhdl/VexRiscv/test/0.0.4/README.md
- curl -X POST -udolu1990:$BINTRAY_KEY https://api.bintray.com/content/spinalhdl/VexRiscv/test/0.0.4/publish
- sbt compile
#- cd VexRiscv
#- curl -T README.md -udolu1990:$BINTRAY_KEY https://api.bintray.com/content/spinalhdl/VexRiscv/test/0.0.4/README.md
#- curl -X POST -udolu1990:$BINTRAY_KEY https://api.bintray.com/content/spinalhdl/VexRiscv/test/0.0.4/publish
#- sbt compile
before_cache:

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@ -11,9 +11,12 @@ EclipseKeys.withSource := true
libraryDependencies ++= Seq(
"com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.6",
"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.6",
"org.scalatest" % "scalatest_2.11" % "2.2.1",
"org.yaml" % "snakeyaml" % "1.8"
)
addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2")
scalacOptions += "-P:continuations:enable"
fork := true

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@ -1,8 +1,13 @@
package vexriscv.demo
import scala.sys.process._
package vexriscv
import java.io.File
object DhrystoneBench extends App{
import org.scalatest.{FunSuite}
import vexriscv.demo._
import scala.sys.process._
class DhrystoneBench extends FunSuite{
def doCmd(cmd : String) : String = {
val stdOut = new StringBuilder()
class Logger extends ProcessLogger {override def err(s: => String): Unit = {if(!s.startsWith("ar: creating ")) println(s)}
@ -16,72 +21,78 @@ object DhrystoneBench extends App{
stdOut.toString()
}
val report = new StringBuilder()
def getDmips(name : String, gen : => Unit, test : String): Unit ={
def getDmips(name : String, gen : => Unit, testCmd : String): Unit = {
test(name + "_gen") {
gen
val str = doCmd(test)
}
test(name + "_test"){
val str = doCmd(testCmd)
assert(!str.contains("FAIL"))
val intFind = "(\\d+\\.?)+".r
val dmips = intFind.findFirstIn("DMIPS per Mhz\\: (\\d+.?)+".r.findAllIn(str).toList.last).get.toDouble
report ++= name + " -> " + dmips + "\n"
}
}
getDmips(
name = "GenSmallestNoCsr",
gen = GenSmallestNoCsr.main(null),
test = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
)
getDmips(
name = "GenSmallest",
gen = GenSmallest.main(null),
test = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
)
getDmips(
name = "GenSmallAndProductive",
gen = GenSmallAndProductive.main(null),
test = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
)
getDmips(
name = "GenSmallAndProductiveWithICache",
gen = GenSmallAndProductiveICache.main(null),
test = "make clean run REDO=10 IBUS=CACHED DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
testCmd = "make clean run REDO=10 IBUS=CACHED DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no"
)
getDmips(
name = "GenFullNoMmuNoCache",
gen = GenFullNoMmuNoCache.main(null),
test = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no"
testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no"
)
getDmips(
name = "GenNoCacheNoMmuMaxPerf",
gen = GenNoCacheNoMmuMaxPerf.main(null),
test = "make clean run REDO=10 MMU=no CSR=no DBUS=SIMPLE IBUS=SIMPLE"
testCmd = "make clean run REDO=10 MMU=no CSR=no DBUS=SIMPLE IBUS=SIMPLE"
)
getDmips(
name = "GenFullNoMmuMaxPerf",
gen = GenFullNoMmuMaxPerf.main(null),
test = "make clean run REDO=10 MMU=no CSR=no"
testCmd = "make clean run REDO=10 MMU=no CSR=no"
)
getDmips(
name = "GenFullNoMmu",
gen = GenFullNoMmu.main(null),
test = "make clean run REDO=10 MMU=no CSR=no"
testCmd = "make clean run REDO=10 MMU=no CSR=no"
)
getDmips(
name = "GenFull",
gen = GenFull.main(null),
test = "make clean run REDO=10 CSR=no MMU=no"
testCmd = "make clean run REDO=10 CSR=no MMU=no"
)
test("final_report") {
println(report)
}
}

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@ -1,117 +0,0 @@
//package vexriscv
//
//import spinal.core._
//import spinal.lib.master
//import vexriscv.ip.InstructionCacheConfig
//import vexriscv.plugin._
//
//object PlayGen extends App{
// def cpu() = new VexRiscv(
// config = VexRiscvConfig(
// plugins = List(
// new IBusCachedPlugin(
// config = InstructionCacheConfig(
// cacheSize = 16,
// bytePerLine = 4,
// wayCount = 1,
// addressWidth = 32,
// cpuDataWidth = 32,
// memDataWidth = 32,
// catchIllegalAccess = false,
// catchAccessFault = false,
// catchMemoryTranslationMiss = false,
// asyncTagMemory = false,
// twoCycleRam = false,
// preResetFlush = false
// )
// ),
// new FormalPlugin,
// new HaltOnExceptionPlugin,
// new PcManagerSimplePlugin(
// resetVector = 0x00000000l,
// relaxedPcCalculation = false
// ),
//// new IBusSimplePlugin(
//// interfaceKeepData = false,
//// catchAccessFault = false
//// ),
// new DBusSimplePlugin(
// catchAddressMisaligned = true,
// catchAccessFault = false
// ),
// new DecoderSimplePlugin(
// catchIllegalInstruction = true,
// forceLegalInstructionComputation = true
// ),
// new RegFilePlugin(
// regFileReadyKind = plugin.SYNC,
// zeroBoot = false
// ),
// new IntAluPlugin,
// new SrcPlugin(
// separatedAddSub = false,
// executeInsertion = false
// ),
// new FullBarrielShifterPlugin,
// new HazardSimplePlugin(
// bypassExecute = false,
// bypassMemory = false,
// bypassWriteBack = false,
// bypassWriteBackBuffer = false,
// pessimisticUseSrc = false,
// pessimisticWriteRegFile = false,
// pessimisticAddressMatch = false
// ),
// new BranchPlugin(
// earlyBranch = false,
// catchAddressMisaligned = true,
// prediction = NONE
// ),
// new YamlPlugin("cpu0.yaml")
// )
// )
// )
// // Wrap with input/output registers
// def wrap(that : => VexRiscv) : Component = {
// val c = that
//// c.rework {
//// for (e <- c.getOrdredNodeIo) {
//// if (e.isInput) {
//// e.asDirectionLess()
//// e := RegNext(RegNext(in(cloneOf(e))))
////
//// } else {
//// e.asDirectionLess()
//// out(cloneOf(e)) := RegNext(RegNext(e))
//// }
//// }
//// }
//
// c.rework{
// c.config.plugins.foreach{
// case p : IBusCachedPlugin => {
// p.iBus.asDirectionLess().unsetName()
// val iBusNew = master(IBusSimpleBus(false)).setName("iBus")
//
// iBusNew.cmd.valid := p.iBus.cmd.valid
// iBusNew.cmd.pc := p.iBus.cmd.address
// p.iBus.cmd.ready := iBusNew.cmd.ready
//
// val pending = RegInit(False) clearWhen(iBusNew.rsp.ready) setWhen (iBusNew.cmd.fire)
// p.iBus.rsp.valid := iBusNew.rsp.ready & pending
// p.iBus.rsp.error := iBusNew.rsp.error
// p.iBus.rsp.data := iBusNew.rsp.inst
// }
// case _ =>
// }
// }
// c
// }
// SpinalConfig(
// defaultConfigForClockDomains = ClockDomainConfig(
// resetKind = spinal.core.SYNC,
// resetActiveLevel = spinal.core.HIGH
// ),
// inlineRom = true
// ).generateVerilog(wrap(cpu()))
//}