Fix target branch prediction for RVC, all default configs pass dhrystone
This commit is contained in:
Charles Papon
parent
a684d5e4d1
commit
59508d5b57
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@ -247,36 +247,42 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val bufferValid = RegInit(False)
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val bufferData = Reg(Bits(16 bits))
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val isInputLowRvc = input.rsp.inst(1 downto 0) =/= 3
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val isInputHighRvc = input.rsp.inst(17 downto 16) =/= 3
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val doubleRvc = iBusRsp.stages.last.input.valid && !bufferValid && isInputLowRvc && isInputHighRvc && !input.pc(1)
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val throw2BytesReg = RegInit(False)
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val throw2Bytes = throw2BytesReg || input.pc(1)
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val unaligned = throw2Bytes || bufferValid
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def aligned = !unaligned
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val raw = Mux(
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sel = bufferValid,
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whenTrue = input.rsp.inst(15 downto 0) ## bufferData,
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whenFalse = input.rsp.inst(31 downto 16) ## (input.pc(1) ? input.rsp.inst(31 downto 16) | input.rsp.inst(15 downto 0))
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whenFalse = input.rsp.inst(31 downto 16) ## (throw2Bytes ? input.rsp.inst(31 downto 16) | input.rsp.inst(15 downto 0))
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)
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val isRvc = raw(1 downto 0) =/= 3
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val isBufferRvc = bufferData(1 downto 0) =/= 3
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val decompressed = RvcDecompressor(raw(15 downto 0))
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output.valid := bufferValid ? (isBufferRvc || input.valid) | (input.valid && (!input.pc(1) || input.rsp.inst(17 downto 16) =/= 3))
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output.valid := input.valid && !(throw2Bytes && !bufferValid && !isInputHighRvc)
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output.pc := input.pc
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output.isRvc := isRvc
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output.rsp.inst := isRvc ? decompressed | raw
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input.ready := output.ready && !(bufferValid && isBufferRvc)
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input.ready := output.ready && (!iBusRsp.stages.last.input.valid || (!(bufferValid && isInputHighRvc) && !(aligned && isInputLowRvc && isInputHighRvc)))
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val bufferFill = False
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when(output.ready && (isBufferRvc || input.valid)){
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when(output.fire){
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throw2BytesReg := (aligned && isInputLowRvc && isInputHighRvc) || (bufferValid && isInputHighRvc)
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}
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val bufferFill = (aligned && isInputLowRvc && !isInputHighRvc) || (bufferValid && !isInputHighRvc) || (throw2Bytes && !isRvc && !isInputHighRvc)
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when(output.ready && input.valid){
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bufferValid := False
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}
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when(output.ready && input.valid){
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bufferData := input.rsp.inst(31 downto 16)
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when((!bufferValid && !input.pc(1) && input.rsp.inst(1 downto 0) =/= 3) || (bufferValid && !isBufferRvc) || (input.pc(1) && input.rsp.inst(17 downto 16) === 3)){
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bufferFill := True
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bufferValid := True
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}
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bufferValid setWhen(bufferFill)
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}
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bufferValid.clearWhen(flush)
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when(bufferValid && isBufferRvc){
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iBusRsp.readyForError := False
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incomingInstruction := True
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when(flush){
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throw2BytesReg := False
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bufferValid := False
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}
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})
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@ -504,7 +510,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val source = Bits(30 - historyRamSizeLog2 bits)
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val branchWish = UInt(2 bits)
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val target = UInt(32 bits)
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val unaligned = ifGen(compressedGen)(Bool)
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val last2Bytes = ifGen(compressedGen)(Bool)
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}
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val history = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
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@ -515,6 +521,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(1).input.payload >> 2).resized
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val line = history.readSync((iBusRsp.stages(0).input.payload >> 2).resized, iBusRsp.stages(0).output.ready)
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val hit = line.source === (iBusRsp.stages(1).input.payload.asBits >> 2 + historyRamSizeLog2)
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if(compressedGen) hit clearWhen(!line.last2Bytes && iBusRsp.stages(1).input.payload(1))
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fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && !hazard && iBusRsp.stages(1).input.valid
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fetchPc.predictionPcLoad.payload := line.target
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@ -533,14 +540,16 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val (decompressorContext, injectorContext) = stage1ToInjectorPipe(fetchContext)
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if(compressedGen) {
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//prediction hit on the right instruction into words
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decompressorContext.hit clearWhen(decompressorContext.line.unaligned && (decompressor.bufferValid || (decompressor.isRvc && !decompressor.input.pc(1))))
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decompressorContext.hit clearWhen(decompressorContext.line.last2Bytes && (decompressor.bufferValid || (decompressor.isRvc && !decompressor.throw2Bytes)))
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decodePc.predictionPcLoad.valid := injectorContext.line.branchWish.msb && injectorContext.hit && !injectorContext.hazard && injector.decodeInput.fire
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decodePc.predictionPcLoad.payload := injectorContext.line.target
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//Clean the RVC buffer when a prediction was made
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when(decompressorContext.line.branchWish.msb && decompressorContext.hit && !decompressorContext.hazard && decompressor.output.fire){
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decompressor.bufferValid := False
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decompressor.input.ready := True
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decompressor.throw2BytesReg := False
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decompressor.input.ready := True //Drop the remaining byte if any
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}
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}
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@ -557,7 +566,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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historyWrite.address := fetchPrediction.rsp.sourceLastWord(2, historyRamSizeLog2 bits)
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historyWrite.data.source := fetchPrediction.rsp.sourceLastWord.asBits >> 2 + historyRamSizeLog2
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historyWrite.data.target := fetchPrediction.rsp.finalPc
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if(compressedGen) historyWrite.data.unaligned := !fetchPrediction.stage.input(PC)(1) ^ fetchPrediction.stage.input(IS_RVC)
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if(compressedGen) historyWrite.data.last2Bytes := fetchPrediction.stage.input(PC)(1) && fetchPrediction.stage.input(IS_RVC)
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when(fetchPrediction.rsp.wasRight) {
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historyWrite.valid := branchContext.hit
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@ -574,18 +583,13 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring)
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val predictionFailure = ifGen(compressedGen)(new Area{
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val predictionBranch = decompressorContext.hit && !decompressorContext.hazard && decompressorContext.line.branchWish(1)
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val unalignedWordIssue = decompressor.bufferFill && decompressor.input.rsp.inst(17 downto 16) === 3 && predictionBranch
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val decompressorFailure = RegInit(False) setWhen(unalignedWordIssue) clearWhen(fetcherflushIt)
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val injectorFailure = Delay(decompressorFailure, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready, init=False)
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val bypassFailure = if(!injectorStage) False else decompressorFailure && !injector.decodeInput.valid
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val unalignedWordIssue = iBusRsp.output.valid && predictionBranch && decompressor.throw2Bytes && !decompressor.isInputHighRvc
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when(injectorFailure || bypassFailure){
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when(unalignedWordIssue){
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historyWrite.valid := True
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historyWrite.address := (decode.input(PC) >> 2).resized
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historyWrite.address := (iBusRsp.stages(1).input.payload >> 2).resized
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historyWrite.data.branchWish := 0
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iBusRsp.redoFetch := True
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