Exclude TCL from the repo
This commit is contained in:
Dolu1990
parent
a38b137db2
commit
59e09ce269
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@ -39,4 +39,5 @@ obj_dir
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*.yaml
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*.yaml
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*.memTrace
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*.memTrace
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*.regTrace
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*.regTrace
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*.tcl
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@ -1,228 +0,0 @@
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package require -exact qsys 13.1
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#
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# module def
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME VexRiscvAvalon
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME VexRiscvAvalon
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE false
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set_module_property ANALYZE_HDL false
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL VexRiscvAvalon
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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#add_fileset_file VexRiscvAvalon.vhd VHDL PATH VexRiscvAvalon.vhd TOP_LEVEL_FILE
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add_fileset SIM_VHDL SIM_VHDL "" ""
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set_fileset_property SIM_VHDL TOP_LEVEL VexRiscvAvalon
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set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
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#add_fileset_file VexRiscvAvalon.vhd VHDL PATH VexRiscvAvalon.vhd
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#
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# connection point debug_resetOut
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#
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add_interface debug_resetOut reset start
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set_interface_property debug_resetOut associatedClock clk
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set_interface_property debug_resetOut associatedDirectReset ""
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set_interface_property debug_resetOut associatedResetSinks ""
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set_interface_property debug_resetOut synchronousEdges DEASSERT
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set_interface_property debug_resetOut ENABLED true
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set_interface_property debug_resetOut EXPORT_OF ""
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set_interface_property debug_resetOut PORT_NAME_MAP ""
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set_interface_property debug_resetOut SVD_ADDRESS_GROUP ""
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add_interface_port debug_resetOut debug_resetOut reset Output 1
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#
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# connection point timerInterrupt
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#
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add_interface timerInterrupt interrupt start
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set_interface_property timerInterrupt associatedAddressablePoint iBusAvalon
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set_interface_property timerInterrupt associatedClock clk
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set_interface_property timerInterrupt associatedReset reset
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set_interface_property timerInterrupt irqScheme INDIVIDUAL_REQUESTS
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set_interface_property timerInterrupt ENABLED true
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set_interface_property timerInterrupt EXPORT_OF ""
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set_interface_property timerInterrupt PORT_NAME_MAP ""
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set_interface_property timerInterrupt SVD_ADDRESS_GROUP ""
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add_interface_port timerInterrupt timerInterrupt irq Input 1
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#
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# connection point externalInterrupt
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#
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add_interface externalInterrupt interrupt start
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set_interface_property externalInterrupt associatedAddressablePoint iBusAvalon
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set_interface_property externalInterrupt associatedClock clk
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set_interface_property externalInterrupt associatedReset reset
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set_interface_property externalInterrupt irqScheme INDIVIDUAL_REQUESTS
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set_interface_property externalInterrupt ENABLED true
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set_interface_property externalInterrupt EXPORT_OF ""
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set_interface_property externalInterrupt PORT_NAME_MAP ""
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set_interface_property externalInterrupt SVD_ADDRESS_GROUP ""
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add_interface_port externalInterrupt externalInterrupt irq Input 1
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#
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# connection point iBusAvalon
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#
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add_interface iBusAvalon avalon start
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set_interface_property iBusAvalon addressUnits SYMBOLS
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set_interface_property iBusAvalon burstcountUnits WORDS
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set_interface_property iBusAvalon burstOnBurstBoundariesOnly false
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set_interface_property iBusAvalon constantBurstBehavior true
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set_interface_property iBusAvalon holdTime 0
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set_interface_property iBusAvalon linewrapBursts true
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set_interface_property iBusAvalon maximumPendingReadTransactions 1
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set_interface_property iBusAvalon maximumPendingWriteTransactions 0
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set_interface_property iBusAvalon readLatency 0
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set_interface_property iBusAvalon readWaitTime 0
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set_interface_property iBusAvalon setupTime 0
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set_interface_property iBusAvalon writeWaitTime 0
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set_interface_property iBusAvalon holdTime 0
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set_interface_property iBusAvalon associatedClock clk
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set_interface_property iBusAvalon associatedReset reset
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set_interface_property iBusAvalon bitsPerSymbol 8
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set_interface_property iBusAvalon timingUnits Cycles
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set_interface_property iBusAvalon ENABLED true
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set_interface_property iBusAvalon EXPORT_OF ""
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set_interface_property iBusAvalon PORT_NAME_MAP ""
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set_interface_property iBusAvalon SVD_ADDRESS_GROUP ""
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set_interface_property iBusAvalon doStreamReads false
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set_interface_property iBusAvalon doStreamWrites false
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add_interface_port iBusAvalon iBusAvalon_address address Output 32
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add_interface_port iBusAvalon iBusAvalon_read read Output 1
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add_interface_port iBusAvalon iBusAvalon_waitRequestn waitrequest_n Input 1
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add_interface_port iBusAvalon iBusAvalon_burstCount burstcount Output 4
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add_interface_port iBusAvalon iBusAvalon_readDataValid readdatavalid Input 1
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add_interface_port iBusAvalon iBusAvalon_readData readdata Input 32
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#
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# connection point dBusAvalon
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#
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add_interface dBusAvalon avalon start
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set_interface_property dBusAvalon addressUnits SYMBOLS
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set_interface_property dBusAvalon burstcountUnits WORDS
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set_interface_property dBusAvalon burstOnBurstBoundariesOnly true
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set_interface_property dBusAvalon constantBurstBehavior true
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set_interface_property dBusAvalon holdTime 0
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set_interface_property dBusAvalon linewrapBursts false
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set_interface_property dBusAvalon maximumPendingReadTransactions 2
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set_interface_property dBusAvalon maximumPendingWriteTransactions 0
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set_interface_property dBusAvalon readLatency 0
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set_interface_property dBusAvalon readWaitTime 0
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set_interface_property dBusAvalon setupTime 0
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set_interface_property dBusAvalon writeWaitTime 0
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set_interface_property dBusAvalon holdTime 0
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set_interface_property dBusAvalon associatedClock clk
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set_interface_property dBusAvalon associatedReset reset
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set_interface_property dBusAvalon bitsPerSymbol 8
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set_interface_property dBusAvalon timingUnits Cycles
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set_interface_property dBusAvalon ENABLED true
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set_interface_property dBusAvalon EXPORT_OF ""
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set_interface_property dBusAvalon PORT_NAME_MAP ""
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set_interface_property dBusAvalon SVD_ADDRESS_GROUP ""
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set_interface_property dBusAvalon doStreamReads false
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set_interface_property dBusAvalon doStreamWrites false
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add_interface_port dBusAvalon dBusAvalon_address address Output 32
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add_interface_port dBusAvalon dBusAvalon_read read Output 1
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add_interface_port dBusAvalon dBusAvalon_write write Output 1
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add_interface_port dBusAvalon dBusAvalon_waitRequestn waitrequest_n Input 1
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add_interface_port dBusAvalon dBusAvalon_burstCount burstcount Output 4
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add_interface_port dBusAvalon dBusAvalon_byteEnable byteenable Output 4
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add_interface_port dBusAvalon dBusAvalon_writeData writedata Output 32
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add_interface_port dBusAvalon dBusAvalon_readDataValid readdatavalid Input 1
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add_interface_port dBusAvalon dBusAvalon_readData readdata Input 32
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#
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# connection point debugBusAvalon
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#
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add_interface debugBusAvalon avalon end
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set_interface_property debugBusAvalon addressUnits SYMBOLS
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set_interface_property debugBusAvalon burstcountUnits WORDS
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set_interface_property debugBusAvalon burstOnBurstBoundariesOnly false
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set_interface_property debugBusAvalon constantBurstBehavior false
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set_interface_property debugBusAvalon holdTime 0
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set_interface_property debugBusAvalon linewrapBursts false
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set_interface_property debugBusAvalon maximumPendingReadTransactions 0
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set_interface_property debugBusAvalon maximumPendingWriteTransactions 0
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set_interface_property debugBusAvalon readLatency 0
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set_interface_property debugBusAvalon readWaitTime 0
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set_interface_property debugBusAvalon setupTime 0
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set_interface_property debugBusAvalon writeWaitTime 0
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set_interface_property debugBusAvalon holdTime 0
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set_interface_property debugBusAvalon associatedClock clk
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set_interface_property debugBusAvalon associatedReset debugReset
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set_interface_property debugBusAvalon bitsPerSymbol 8
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set_interface_property debugBusAvalon timingUnits Cycles
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set_interface_property debugBusAvalon ENABLED true
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set_interface_property debugBusAvalon EXPORT_OF ""
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set_interface_property debugBusAvalon PORT_NAME_MAP ""
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set_interface_property debugBusAvalon SVD_ADDRESS_GROUP ""
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add_interface_port debugBusAvalon debugBusAvalon_address address Input 8
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add_interface_port debugBusAvalon debugBusAvalon_read read Input 1
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add_interface_port debugBusAvalon debugBusAvalon_write write Input 1
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add_interface_port debugBusAvalon debugBusAvalon_waitRequestn waitrequest_n Output 1
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add_interface_port debugBusAvalon debugBusAvalon_writeData writedata Input 32
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add_interface_port debugBusAvalon debugBusAvalon_readData readdata Output 32
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#
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# connection point clk
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#
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add_interface clk clock end
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set_interface_property clk clockRate 0
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set_interface_property clk ENABLED true
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set_interface_property clk EXPORT_OF ""
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set_interface_property clk PORT_NAME_MAP ""
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set_interface_property clk SVD_ADDRESS_GROUP ""
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add_interface_port clk clk clk Input 1
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#
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# connection point debugReset
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#
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add_interface debugReset reset end
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set_interface_property debugReset associatedClock clk
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set_interface_property debugReset synchronousEdges DEASSERT
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set_interface_property debugReset ENABLED true
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set_interface_property debugReset EXPORT_OF ""
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set_interface_property debugReset PORT_NAME_MAP ""
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set_interface_property debugReset SVD_ADDRESS_GROUP ""
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add_interface_port debugReset debugReset reset Input 1
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#
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# connection point reset
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#
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add_interface reset reset end
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set_interface_property reset associatedClock clk
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set_interface_property reset synchronousEdges DEASSERT
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set_interface_property reset ENABLED true
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set_interface_property reset EXPORT_OF ""
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set_interface_property reset PORT_NAME_MAP ""
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set_interface_property reset SVD_ADDRESS_GROUP ""
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add_interface_port reset reset reset Input 1
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54
backup
54
backup
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@ -1,54 +0,0 @@
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class PcManagerSimple(resetVector : BigInt,pcWidth : Int,fastFetchCmdPcCalculation : Boolean) extends Plugin[SpinalRiscv] with PcManagerService{
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import StandardStageables._
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//FetchService interface
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case class JumpInfo(pc: UInt, cond: Bool, stage: Stage)
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val jumpInfos = ArrayBuffer[JumpInfo]()
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override def jumpTo(pc: UInt, cond: Bool, stage: Stage): Unit = jumpInfos += JumpInfo(pc,cond,stage)
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override def build(pipeline: SpinalRiscv): Unit = {
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import pipeline.prefetch
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prefetch.plug(new Area {
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import prefetch._
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//PC calculation without Jump
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val pcReg = Reg(UInt(pcWidth bit)) init(resetVector)
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val inc = RegInit(False)
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val pc = if(fastFetchCmdPcCalculation){
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val pcPlus4 = pcReg + 4
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pcPlus4.addAttribute("keep")
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Mux(inc,pcPlus4,pcReg)
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}else{
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pcReg + (inc ? U(4) | U(0))
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}
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//Stage always valid
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arbitration.isValid := True
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//FetchService hardware implementation
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val jumpInfoSorted = jumpInfos.sortWith((a,b) => pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage))
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val jumpRequestValids = jumpInfoSorted.map(_.cond)
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val jumpRequestPcs = jumpInfoSorted.map(_.pc)
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val pcLoad = Flow(pcReg)
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pcLoad.valid := jumpInfos.foldLeft(False)(_ || _.cond)
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pcLoad.payload := MuxOH(jumpRequestValids,jumpRequestPcs)
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//Register managments
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when(pcLoad.valid){
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pc := pcLoad.payload
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inc := False
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pcReg := pc
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}
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when(arbitration.isFiring){
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inc := True
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pcReg := pc
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}
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//Pipeline insertions
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insert(PC) := pc
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})
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}
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}
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