fpu improve pipline cycles

src/main/scala/vexriscv/ip/fpu/FpuCore.scala

@@ -185,7 +185,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
       val fork = new StreamFork(FpuCommit(p), 2, synchronous = true)
       fork.io.input << io.port(i).commit
       fork.io.outputs(0) >> load(i)
-      fork.io.outputs(1).pipelined(m2s = true, s2m = true) >> commit(i) //Pipelining here is light, as it only use the flags of the payload
+      fork.io.outputs(1).pipelined(m2s = false, s2m = true) >> commit(i) //Pipelining here is light, as it only use the flags of the payload
     }
   }
 
@@ -417,7 +417,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
     }
 
     val s0 = new Area{
-      val input = decode.load.pipelined(m2s = true, s2m = true)
+      val input = decode.load.pipelined(m2s = true, s2m = true).stage()
       val filtred = commitFork.load.map(port => port.takeWhen(List(FpuOpcode.LOAD, FpuOpcode.FMV_W_X, FpuOpcode.I2F).map(_ === port.opcode).orR))
       def feed = filtred(input.source)
       val hazard = !feed.valid

src/main/scala/vexriscv/plugin/FpuPlugin.scala

@@ -267,7 +267,7 @@ class FpuPlugin(externalFpu : Boolean = false,
       val fs = Reg(Bits(2 bits)) init(1)
       val sd = fs === 3
 
-      when(stages.last.arbitration.isFiring && stages.last.input(FPU_ENABLE)){
+      when(stages.last.arbitration.isFiring && stages.last.input(FPU_ENABLE) && stages.last.input(FPU_OPCODE) =/= FpuOpcode.STORE){
         fs := 3 //DIRTY
       }
 
@@ -349,7 +349,7 @@ class FpuPlugin(externalFpu : Boolean = false,
         arbitration.haltByOther := True
       }
 
-      port.commit <-/< commit
+      port.commit << commit.pipelined(s2m = true, m2s = false)
     }
 
     pipeline.stages.dropRight(1).foreach(s => s.output(FPU_FORKED) clearWhen(s.arbitration.isStuck))