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A few plugins config are now var

This commit is contained in:
Dolu1990 2023-03-22 11:06:56 +01:00
parent 4972a27ae9
commit 5b47564024
4 changed files with 4 additions and 4 deletions
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2
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -81,7 +81,7 @@ case class CsrPluginConfig(
csrOhDecoder : Boolean = true, csrOhDecoder : Boolean = true,
deterministicInteruptionEntry : Boolean = false, //Only used for simulatation purposes deterministicInteruptionEntry : Boolean = false, //Only used for simulatation purposes
wfiOutput : Boolean = false, wfiOutput : Boolean = false,
withPrivilegedDebug : Boolean = false, //For the official RISC-V debug spec implementation var withPrivilegedDebug : Boolean = false, //For the official RISC-V debug spec implementation
var debugTriggers : Int = 2 var debugTriggers : Int = 2
){ ){
assert(!ucycleAccess.canWrite) assert(!ucycleAccess.canWrite)

2
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
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@ -48,7 +48,7 @@ case class TightlyCoupledDataPort(p : TightlyCoupledDataPortParameter, var bus :
class DBusCachedPlugin(val config : DataCacheConfig, class DBusCachedPlugin(val config : DataCacheConfig,
memoryTranslatorPortConfig : Any = null, memoryTranslatorPortConfig : Any = null,
dBusCmdMasterPipe : Boolean = false, var dBusCmdMasterPipe : Boolean = false,
dBusCmdSlavePipe : Boolean = false, dBusCmdSlavePipe : Boolean = false,
dBusRspSlavePipe : Boolean = false, dBusRspSlavePipe : Boolean = false,
relaxedMemoryTranslationRegister : Boolean = false, relaxedMemoryTranslationRegister : Boolean = false,

2
src/main/scala/vexriscv/plugin/Fetcher.scala
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@ -11,7 +11,7 @@ import scala.collection.mutable.ArrayBuffer
//TODO val killLastStage = jump.pcLoad.valid || decode.arbitration.isRemoved //TODO val killLastStage = jump.pcLoad.valid || decode.arbitration.isRemoved
// DBUSSimple check memory halt execute optimization // DBUSSimple check memory halt execute optimization
abstract class IBusFetcherImpl(val resetVector : BigInt, abstract class IBusFetcherImpl(var resetVector : BigInt,
val keepPcPlus4 : Boolean, val keepPcPlus4 : Boolean,
val decodePcGen : Boolean, val decodePcGen : Boolean,
val compressedGen : Boolean, val compressedGen : Boolean,

2
src/main/scala/vexriscv/plugin/FpuPlugin.scala
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@ -23,7 +23,7 @@ class FpuAcessPort(val p : FpuParameter) extends Bundle{
} }
class FpuPlugin(externalFpu : Boolean = false, class FpuPlugin(externalFpu : Boolean = false,
simHalt : Boolean = false, var simHalt : Boolean = false,
val p : FpuParameter) extends Plugin[VexRiscv] with VexRiscvRegressionArg { val p : FpuParameter) extends Plugin[VexRiscv] with VexRiscvRegressionArg {
object FPU_ENABLE extends Stageable(Bool()) object FPU_ENABLE extends Stageable(Bool())