DYNAMIC_TARGET prediction datapath/control path are now splited
This commit is contained in:
Charles Papon
parent
0e95154869
commit
5b53440d27
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@ -103,7 +103,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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pcLoad.payload := MuxOH(OHMasking.first(valids.asBits), pcs)
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}
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def flush = fetcherflushIt || stages.map(_.arbitration.flushNext).orR
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fetcherflushIt setWhen(stages.map(_.arbitration.flushNext).orR)
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class PcFetch extends Area{
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val preOutput = Stream(UInt(32 bits))
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@ -225,12 +225,12 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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}
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for((s,sNext) <- (stages, stages.tail).zipped) {
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if(s == stages.head && pcRegReusedForSecondStage) {
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sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(flush, s != stages.head, collapsBubble = false))
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if(s == stages.head && pcRegReusedForSecondStage && prediction != DYNAMIC_TARGET) { //DYNAMIC_TARGET realy need PC state for both stage(0) and stage(1)
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sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(fetcherflushIt, s != stages.head, collapsBubble = false))
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sNext.input.payload := fetchPc.pcReg
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fetchPc.propagatePc setWhen(sNext.input.fire)
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} else {
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sNext.input << s.output.m2sPipeWithFlush(flush, s != stages.head, collapsBubble = false)
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sNext.input << s.output.m2sPipeWithFlush(fetcherflushIt, s != stages.head, collapsBubble = false)
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}
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}
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@ -273,7 +273,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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// input.ready := (bufferValid ? (!isRvc && output.ready) | (input.pc(1) || output.ready))
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input.ready := !output.valid || !(!output.ready || (isRvc && !input.pc(1) && input.rsp.inst(16, 2 bits) =/= 3) || (!isRvc && bufferValid && input.rsp.inst(16, 2 bits) =/= 3))
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addPrePopTask(() => {
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when(!input.ready && output.fire && !flush /* && ((isRvc && !bufferValid && !input.pc(1)) || (!isRvc && bufferValid && input.rsp.inst(16, 2 bits) =/= 3))*/) {
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when(!input.ready && output.fire && !fetcherflushIt /* && ((isRvc && !bufferValid && !input.pc(1)) || (!isRvc && bufferValid && input.rsp.inst(16, 2 bits) =/= 3))*/) {
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input.pc.getDrivingReg(1) := True
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}
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})
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@ -284,7 +284,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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bufferValid := !(!isRvc && !input.pc(1) && !bufferValid) && !(isRvc && input.pc(1) && output.ready)
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bufferData := input.rsp.inst(31 downto 16)
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}
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bufferValid.clearWhen(flush)
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bufferValid.clearWhen(fetcherflushIt)
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iBusRsp.readyForError.clearWhen(bufferValid && isRvc) //Can't emit error, as there is a earlier instruction pending
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incomingInstruction setWhen(bufferValid && bufferData(1 downto 0) =/= 3)
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})
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@ -292,13 +292,13 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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def condApply[T](that : T, cond : Boolean)(func : (T) => T) = if(cond)func(that) else that
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val injector = new Area {
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val inputBeforeStage = condApply(if (decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(flush))
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val inputBeforeStage = condApply(if (decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(fetcherflushIt))
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if (injectorReadyCutGen) {
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iBusRsp.readyForError.clearWhen(inputBeforeStage.valid) //Can't emit error if there is a instruction pending in the s2mPipe
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incomingInstruction setWhen (inputBeforeStage.valid)
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}
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val decodeInput = (if (injectorStage) {
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val decodeInput = inputBeforeStage.m2sPipeWithFlush(flush, collapsBubble = false)
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val decodeInput = inputBeforeStage.m2sPipeWithFlush(fetcherflushIt, collapsBubble = false)
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeStage.rsp.inst)
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iBusRsp.readyForError.clearWhen(decodeInput.valid) //Can't emit error when there is a instruction pending in the injector stage buffer
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incomingInstruction setWhen (decodeInput.valid)
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@ -313,13 +313,13 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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def pcUpdatedGen(input : Bool, stucks : Seq[Bool], relaxedInput : Boolean) : Seq[Bool] = {
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stucks.scanLeft(input)((i, stuck) => {
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val reg = RegInit(False)
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if(!relaxedInput) when(flush) {
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if(!relaxedInput) when(fetcherflushIt) {
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reg := False
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}
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when(!stuck) {
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reg := i
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}
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if(relaxedInput || i != input) when(flush) {
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if(relaxedInput || i != input) when(fetcherflushIt) {
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reg := False
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}
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reg
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@ -335,7 +335,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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pcValids := Vec(valids.takeRight(stages.size))
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}
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val decodeRemoved = RegInit(False) setWhen(decode.arbitration.isRemoved) clearWhen(flush) //!decode.arbitration.isStuck || decode.arbitration.isFlushed
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val decodeRemoved = RegInit(False) setWhen(decode.arbitration.isRemoved) clearWhen(fetcherflushIt) //!decode.arbitration.isStuck || decode.arbitration.isFlushed
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decodeInput.ready := !decode.arbitration.isStuck
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decode.arbitration.isValid := decodeInput.valid && !decodeRemoved
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@ -461,7 +461,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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}
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val fetchContext = DynamicContext()
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fetchContext.hazard := hazard
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fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.stages(0).output.ready || flush)
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fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.stages(0).output.ready || fetcherflushIt)
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object PREDICTION_CONTEXT extends Stageable(DynamicContext())
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decode.insert(PREDICTION_CONTEXT) := stage1ToInjectorPipe(fetchContext)._2
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@ -500,17 +500,13 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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}
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//TODO no more fireing depedancies
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predictionJumpInterface.valid := decodePrediction.cmd.hadBranch && decode.arbitration.isValid //TODO OH Doublon de priorité
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predictionJumpInterface.valid := decode.arbitration.isValid && decodePrediction.cmd.hadBranch //TODO OH Doublon de priorité
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predictionJumpInterface.payload := decode.input(PC) + ((decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL) ? imm.j_sext | imm.b_sext).asUInt
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if(relaxPredictorAddress) KeepAttribute(predictionJumpInterface.payload)
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when(predictionJumpInterface.valid && decode.arbitration.isFiring){
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flushIt()
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}
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// when(predictionJumpInterface.payload((if(pipeline(RVC_GEN)) 0 else 1) downto 0) =/= 0){
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// decodePrediction.cmd.hadBranch := False
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// }
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}
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case DYNAMIC_TARGET => new Area{
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// assert(!compressedGen || cmdToRspStageCount == 1, "Can't combine DYNAMIC_TARGET and RVC as it could stop the instruction fetch mid-air")
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@ -525,7 +521,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val history = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
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val historyWrite = history.writePort
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val line = history.readSync((iBusRsp.stages(0).input.payload >> 2).resized, iBusRsp.stages(0).output.ready || flush)
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val line = history.readSync((iBusRsp.stages(0).input.payload >> 2).resized, iBusRsp.stages(0).output.ready || fetcherflushIt)
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val hit = line.source === (iBusRsp.stages(1).input.payload.asBits >> 2 + historyRamSizeLog2) && (if(compressedGen)(!(!line.unaligned && iBusRsp.stages(1).input.payload(1))) else True)
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//Avoid stoping instruction fetch in the middle patch
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@ -537,7 +533,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready)
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val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(1).input.payload >> 2).resized
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//TODO improve predictionPcLoad way of doing things
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fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && !hazard && iBusRsp.stages(1).output.fire //XXX && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))
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fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && !hazard && iBusRsp.stages(1).output.valid //XXX && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))
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fetchPc.predictionPcLoad.payload := line.target
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case class PredictionResult() extends Bundle{
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@ -605,7 +601,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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when(decompressor.input.fire){
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decompressorFailure := decompressorContext.hit && !decompressorContext.hazard && !decompressor.output.valid && decompressorContext.line.branchWish(1)
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}
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decompressorFailure clearWhen(flush || decompressor.output.fire)
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decompressorFailure clearWhen(fetcherflushIt || decompressor.output.fire)
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val injectorFailure = Delay(decompressorFailure, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready)
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@ -151,7 +151,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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stages(0).halt setWhen (cache.io.cpu.prefetch.haltIt)
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cache.io.cpu.fetch.isRemoved := flush
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cache.io.cpu.fetch.isRemoved := fetcherflushIt
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}
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@ -284,7 +284,7 @@ class IBusSimplePlugin(resetVector : BigInt,
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mmuBus.cmd.isValid := cmdForkStage.input.valid
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mmuBus.cmd.virtualAddress := cmdForkStage.input.payload
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mmuBus.cmd.bypassTranslation := False
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mmuBus.end := cmdForkStage.output.fire || flush
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mmuBus.end := cmdForkStage.output.fire || fetcherflushIt
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cmd.pc := mmuBus.rsp.physicalAddress(31 downto 2) @@ "00"
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@ -311,7 +311,7 @@ class IBusSimplePlugin(resetVector : BigInt,
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//Manage flush for iBus transactions in flight
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val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
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discardCounter := discardCounter - (iBus.rsp.fire && discardCounter =/= 0).asUInt
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when(flush) {
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when(fetcherflushIt) {
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if(secondStagePersistence)
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discardCounter := pendingCmd + cmd.valid.asUInt - iBus.rsp.fire.asUInt
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else
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@ -323,7 +323,7 @@ class IBusSimplePlugin(resetVector : BigInt,
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val rspBuffer = if(!rspHoldValue) new Area{
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val c = StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0))
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c.io.push << iBus.rsp.throwWhen(discardCounter =/= 0).toStream
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c.io.flush := flush
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c.io.flush := fetcherflushIt
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rspBufferOutput << c.io.pop
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} else new Area{
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val rspStream = iBus.rsp.throwWhen(discardCounter =/= 0).toStream
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