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Tom Verbeure
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README.md
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README.md
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## Description
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This repository host an RISC-V implementation written in SpinalHDL. There is some specs :
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This repository hosts a RISC-V implementation written in SpinalHDL. Here are some specs :
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- RV32I[M] instruction set
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- Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
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- Pipelined with 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
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- 1.44 DMIPS/Mhz when all features are enabled
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- Optimized for FPGA, fully portable
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- AXI4 and Avalon ready
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- Optional MUL/DIV extension
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- Optional MUL/DIV extensions
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- Optional instruction and data caches
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- Optional MMU
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- Optional debug extension allowing eclipse debugging via an GDB >> openOCD >> JTAG connection
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- Optional interrupts and exception handling with the Machine and the User mode from the riscv-privileged-v1.9.1 spec.
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- Two implementation of shift instructions, Single cycle / shiftNumber cycles
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- Each stage could have bypass or interlock hazard logic
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- FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV
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- The data cache support atomic LR/SC
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- RV32 compressed instruction are supported in the reworkFetch branch for configurations without instruction cache (will be merge in master, WIP)
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- Optional debug extension allowing Eclipse debugging via a GDB >> openOCD >> JTAG connection
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- Optional interrupts and exception handling with Machine and User modes as defined in the [RISC-V Privileged ISA Specification v1.9](https://riscv.org/specifications/privileged-isa/).
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- Two implementations of shift instructions: Single cycle and shiftNumber cycles
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- Each stage can have optional bypass or interlock hazard logic
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- [FreeRTOS port](https://github.com/Dolu1990/FreeRTOS-RISCV)
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- The data cache supports atomic LR/SC
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- Optional RV32 compressed instruction support in the reworkFetch branch for configurations without instruction cache (will be merge in master, WIP)
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The hardware description of this CPU is done by using an very software oriented approach
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(without any overhead in the generated hardware). There is a list of software concepts used :
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The hardware description of this CPU is done by using a very software oriented approach
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(without any overhead in the generated hardware). Here is a list of software concepts used:
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- There is very few fixed things. Nearly everything is plugin based. The PC manager is a plugin, the register file is a plugin, the hazard controller is a plugin ...
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- There is an automatic a tool which allow plugins to insert data in the pipeline at a given stage, and allow other plugins to read it in another stages through automatic pipelining.
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- There is an service system which provide a very dynamic framework. As instance, a plugin could provide an exception service which could then be used by others plugins to emit exceptions from the pipeline.
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- There is an automatic a tool which allows plugins to insert data in the pipeline at a given stage, and allows other plugins to read it in another stage through automatic pipelining.
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- There is an service system which provides a very dynamic framework. For instance, a plugin could provide an exception service which can then be used by other plugins to emit exceptions from the pipeline.
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There is a gitter channel for all questions about VexRiscv :<br>
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[](https://gitter.im/SpinalHDL/VexRiscv?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
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For commercial support, please contact spinalhdl@gmail.com
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For commercial support, please contact spinalhdl@gmail.com.
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## Area usage and maximal frequency
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The following number where obtains by synthesis the CPU as toplevel without any specific synthesis option to save area or to get better maximal frequency (neutral).<br>
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The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral).<br>
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The clock constraint is set to a unattainable value, which tends to increase the design area.<br>
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The dhrystone benchmark were compiled with -O3 -fno-inline<br>
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All the cached configuration have some cache trashing during the dhrystone benchmark except the `VexRiscv full max perf` one. This of course reduce the performance. It is possible to produce dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case.<br>
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The used CPU corresponding configuration can be find in src/scala/vexriscv/demo.
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The dhrystone benchmark was compiled with the `-O3 -fno-inline` option.<br>
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All the cached configurations have some cache trashing during the dhrystone benchmark except the `VexRiscv full max perf` one. This of course reduces the performance. It is possible to produce
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dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case.<br>
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The CPU configurations used below can be found in the `src/scala/vexriscv/demo` directory.
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```
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VexRiscv smallest (RV32I, 0.52 DMIPS/Mhz, no datapath bypass, no interrupt) ->
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@ -108,7 +109,7 @@ VexRiscv full with MMU (RV32IM, 1.26 DMIPS/Mhz with cache trashing, 4KB-I$, 4KB-
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Cyclone IV -> 100 Mhz 2,976 LUT 2,201 FF
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```
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There is a summary of the configuration which produce 1.44 DMIPS :
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The following configuration results in 1.44 DMIPS/MHz:
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- 5 stage : F -> D -> E -> M -> WB
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- single cycle ADD/SUB/Bitwise/Shift ALU
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@ -116,7 +117,7 @@ There is a summary of the configuration which produce 1.44 DMIPS :
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- memory load values are bypassed in the WB stage (late result)
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- 33 cycle division with bypassing in the M stage (late result)
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- single cycle multiplication with bypassing in the WB stage (late result)
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- dynamic branch prediction done in the F stage with an direct mapped target buffer cache (no penalities on corrects predictions)
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- dynamic branch prediction done in the F stage with an direct mapped target buffer cache (no penalties on correct predictions)
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## Dependencies
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@ -150,14 +151,11 @@ sudo make install
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```
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## CPU generation
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You can find two example of CPU instantiation in :
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You can find two example CPU instances in:
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- src/main/scala/vexriscv/GenFull.scala
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- src/main/scala/vexriscv/GenSmallest.scala
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To generate the corresponding RTL as a VexRiscv.v file, run (it could take time the first time you run it):
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NOTE :
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The VexRiscv could need the unreleased master-head of SpinalHDL. If it fail to compile, just get the SpinalHDL repository and do a "sbt clean compile publish-local" in it as described in the dependencies chapter.
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To generate the corresponding RTL as a VexRiscv.v file, run:
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```sh
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sbt "run-main vexriscv.demo.GenFull"
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@ -166,6 +164,11 @@ sbt "run-main vexriscv.demo.GenFull"
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sbt "run-main vexriscv.demo.GenSmallest"
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```
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NOTES:
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- it could take time the first time you run it
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- The VexRiscv could need the unreleased master-head of SpinalHDL. If it fails to compile, just get the SpinalHDL repository and
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do a "sbt clean compile publish-local" in it as described in the dependencies chapter.
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## Regression tests
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To run tests (need the verilator simulator), go in the src/test/cpp/regression folder and run :
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