Add MuraxCfu
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@ -335,6 +335,54 @@ object Murax{
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}
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}
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object MuraxCfu{
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def main(args: Array[String]) {
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SpinalVerilog{
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val config = MuraxConfig.default
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config.cpuPlugins += new CfuPlugin(
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stageCount = 1,
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allowZeroLatency = true,
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encodings = List(
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CfuPluginEncoding (
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instruction = M"-------------------------0001011",
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functionId = List(14 downto 12),
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input2Kind = CfuPlugin.Input2Kind.RS
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)
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),
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busParameter = CfuBusParameter(
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CFU_VERSION = 0,
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CFU_INTERFACE_ID_W = 0,
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CFU_FUNCTION_ID_W = 3,
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CFU_REORDER_ID_W = 0,
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CFU_REQ_RESP_ID_W = 0,
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CFU_INPUTS = 2,
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CFU_INPUT_DATA_W = 32,
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CFU_OUTPUTS = 1,
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CFU_OUTPUT_DATA_W = 32,
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CFU_FLOW_REQ_READY_ALWAYS = false,
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CFU_FLOW_RESP_READY_ALWAYS = false,
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CFU_WITH_STATUS = true,
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CFU_RAW_INSN_W = 32,
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CFU_CFU_ID_W = 4,
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CFU_STATE_INDEX_NUM = 5
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)
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)
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val toplevel = Murax(config)
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toplevel.rework {
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for (plugin <- toplevel.system.cpu.plugins) plugin match {
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case plugin: CfuPlugin => plugin.bus.toIo().setName("miaou")
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case _ =>
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}
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}
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toplevel
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}
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}
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}
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object Murax_iCE40_hx8k_breakout_board_xip{
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case class SB_GB() extends BlackBox{
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