Add LitexSmpDevCluster with per cpu dedicated litedram ports
This commit is contained in:
Dolu1990
parent
bc4a2c3747
commit
5e5c730959
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@ -0,0 +1,242 @@
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package vexriscv.demo.smp
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import spinal.core._
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import spinal.lib.bus.bmb._
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import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig, WishboneSlaveFactory}
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import spinal.lib.com.jtag.Jtag
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import spinal.lib._
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import spinal.lib.bus.bmb.sim.{BmbMemoryMultiPort, BmbMemoryTester}
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import spinal.lib.bus.misc.{AddressMapping, DefaultMapping, SizeMapping}
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import spinal.lib.eda.bench.Bench
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import spinal.lib.misc.Clint
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import spinal.lib.sim.{SimData, SparseMemory, StreamDriver, StreamMonitor, StreamReadyRandomizer}
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import vexriscv.demo.smp.VexRiscvLitexSmpClusterOpenSbi.{cpuCount, parameter}
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import vexriscv.demo.smp.VexRiscvSmpClusterGen.vexRiscvConfig
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import vexriscv.{VexRiscv, VexRiscvConfig}
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import vexriscv.plugin.{CsrPlugin, DBusCachedPlugin, DebugPlugin, IBusCachedPlugin}
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import scala.collection.mutable
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import scala.util.Random
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case class LiteDramNativeParameter(addressWidth : Int, dataWidth : Int)
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case class LiteDramNativeCmd(p : LiteDramNativeParameter) extends Bundle{
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val we = Bool()
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val addr = UInt(p.addressWidth bits)
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}
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case class LiteDramNativeWData(p : LiteDramNativeParameter) extends Bundle{
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val data = Bits(p.dataWidth bits)
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val we = Bits(p.dataWidth/8 bits)
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}
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case class LiteDramNativeRData(p : LiteDramNativeParameter) extends Bundle{
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val data = Bits(p.dataWidth bits)
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}
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case class LiteDramNative(p : LiteDramNativeParameter) extends Bundle with IMasterSlave {
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val cmd = Stream(LiteDramNativeCmd(p))
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val wdata = Stream(LiteDramNativeWData(p))
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val rdata = Stream(LiteDramNativeRData(p))
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override def asMaster(): Unit = {
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master(cmd, wdata)
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slave(rdata)
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}
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def fromBmb(bmb : Bmb, wdataFifoSize : Int, rdataFifoSize : Int) = {
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val bridge = BmbToLiteDram(
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bmbParameter = bmb.p,
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liteDramParameter = this.p,
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wdataFifoSize = wdataFifoSize,
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rdataFifoSize = rdataFifoSize
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)
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bridge.io.input << bmb
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bridge.io.output <> this
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bridge
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}
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def simSlave(ram : SparseMemory,cd : ClockDomain, bmb : Bmb = null): Unit ={
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import spinal.core.sim._
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def bus = this
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case class Cmd(address : Long, we : Boolean)
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case class WData(data : BigInt, we : Long)
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val cmdQueue = mutable.Queue[Cmd]()
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val wdataQueue = mutable.Queue[WData]()
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val rdataQueue = mutable.Queue[BigInt]()
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case class Ref(address : Long, data : BigInt, we : Long, time : Long)
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val ref = mutable.Queue[Ref]()
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if(bmb != null) StreamMonitor(bmb.cmd, cd){p =>
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if(bmb.cmd.opcode.toInt == 1) ref.enqueue(Ref(p.fragment.address.toLong, p.fragment.data.toBigInt, p.fragment.mask.toLong, simTime()))
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}
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var writeCmdCounter, writeDataCounter = 0
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StreamReadyRandomizer(bus.cmd, cd).factor = 0.5f
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StreamMonitor(bus.cmd, cd) { t =>
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cmdQueue.enqueue(Cmd(t.addr.toLong * (p.dataWidth/8) , t.we.toBoolean))
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if(t.we.toBoolean) writeCmdCounter += 1
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}
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StreamReadyRandomizer(bus.wdata, cd).factor = 0.5f
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StreamMonitor(bus.wdata, cd) { p =>
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writeDataCounter += 1
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// if(p.data.toBigInt == BigInt("00000002000000020000000200000002",16)){
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// println("ASD")
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// }
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wdataQueue.enqueue(WData(p.data.toBigInt, p.we.toLong))
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}
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// new SimStreamAssert(cmd,cd)
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// new SimStreamAssert(wdata,cd)
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// new SimStreamAssert(rdata,cd)
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cd.onSamplings{
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if(writeDataCounter-writeCmdCounter > 2){
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println("miaou")
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}
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if(cmdQueue.nonEmpty && Random.nextFloat() < 0.5){
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val cmd = cmdQueue.head
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if(cmd.we){
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if(wdataQueue.nonEmpty){
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// if(cmd.address == 0xc02ae850l) {
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// println(s"! $writeCmdCounter $writeDataCounter")
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// }
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cmdQueue.dequeue()
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val wdata = wdataQueue.dequeue()
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val raw = wdata.data.toByteArray
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val left = wdata.data.toByteArray.size-1
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if(bmb != null){
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assert(ref.nonEmpty)
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assert((ref.head.address & 0xFFFFFFF0l) == cmd.address)
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assert(ref.head.data == wdata.data)
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assert(ref.head.we == wdata.we)
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ref.dequeue()
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}
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// if(cmd.address == 0xc02ae850l) {
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// println(s"$cmd $wdata ${simTime()}")
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// }
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for(i <- 0 until p.dataWidth/8){
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if(((wdata.we >> i) & 1) != 0) {
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// if(cmd.address == 0xc02ae850l) {
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// println(s"W $i ${ if (left - i >= 0) raw(left - i) else 0}")
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// }
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ram.write(cmd.address + i, if (left - i >= 0) raw(left - i) else 0)
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}
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}
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}
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} else {
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cmdQueue.dequeue()
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val value = new Array[Byte](p.dataWidth/8+1)
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val left = value.size-1
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for(i <- 0 until p.dataWidth/8) {
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value(left-i) = ram.read(cmd.address+i)
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}
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rdataQueue.enqueue(BigInt(value))
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}
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}
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}
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StreamDriver(bus.rdata, cd){ p =>
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if(rdataQueue.isEmpty){
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false
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} else {
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p.data #= rdataQueue.dequeue()
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true
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}
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}
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}
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}
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case class BmbToLiteDram(bmbParameter : BmbParameter,
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liteDramParameter : LiteDramNativeParameter,
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wdataFifoSize : Int,
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rdataFifoSize : Int) extends Component{
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val io = new Bundle {
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val input = slave(Bmb(bmbParameter))
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val output = master(LiteDramNative(liteDramParameter))
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}
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val resized = io.input.resize(liteDramParameter.dataWidth)
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val unburstified = resized.unburstify()
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case class Context() extends Bundle {
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val context = Bits(unburstified.p.contextWidth bits)
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val source = UInt(unburstified.p.sourceWidth bits)
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val isWrite = Bool()
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}
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assert(isPow2(rdataFifoSize))
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val pendingRead = Reg(UInt(log2Up(rdataFifoSize) + 1 bits)) init(0)
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val halt = Bool()
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val (cmdFork, dataFork) = StreamFork2(unburstified.cmd.haltWhen(halt))
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val outputCmd = Stream(LiteDramNativeCmd(liteDramParameter))
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outputCmd.arbitrationFrom(cmdFork.haltWhen(pendingRead.msb))
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outputCmd.addr := (cmdFork.address >> log2Up(liteDramParameter.dataWidth/8)).resized
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outputCmd.we := cmdFork.isWrite
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io.output.cmd <-< outputCmd
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if(bmbParameter.canWrite) {
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val wData = Stream(LiteDramNativeWData(liteDramParameter))
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wData.arbitrationFrom(dataFork.throwWhen(dataFork.isRead))
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wData.data := dataFork.data
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wData.we := dataFork.mask
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io.output.wdata << wData.queueLowLatency(wdataFifoSize, latency = 1) //TODO queue low latency
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} else {
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dataFork.ready := True
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io.output.wdata.valid := False
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io.output.wdata.data.assignDontCare()
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io.output.wdata.we.assignDontCare()
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}
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val cmdContext = Stream(Context())
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cmdContext.valid := unburstified.cmd.fire
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cmdContext.context := unburstified.cmd.context
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cmdContext.source := unburstified.cmd.source
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cmdContext.isWrite := unburstified.cmd.isWrite
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halt := !cmdContext.ready
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val rspContext = cmdContext.queue(rdataFifoSize)
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val rdataFifo = io.output.rdata.queueLowLatency(rdataFifoSize, latency = 1)
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rdataFifo.ready := unburstified.rsp.fire && !rspContext.isWrite
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rspContext.ready := unburstified.rsp.fire
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unburstified.rsp.valid := rspContext.valid && (rspContext.isWrite || rdataFifo.valid)
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unburstified.rsp.setSuccess()
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unburstified.rsp.last := True
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unburstified.rsp.source := rspContext.source
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unburstified.rsp.context := rspContext.context
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unburstified.rsp.data := rdataFifo.data
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pendingRead := pendingRead + U(outputCmd.fire && !outputCmd.we) - U(rdataFifo.fire)
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}
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object BmbToLiteDramTester extends App{
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import spinal.core.sim._
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SimConfig.withWave.compile(BmbToLiteDram(
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bmbParameter = BmbParameter(
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addressWidth = 20,
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dataWidth = 32,
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lengthWidth = 6,
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sourceWidth = 4,
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contextWidth = 16
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),
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liteDramParameter = LiteDramNativeParameter(
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addressWidth = 20,
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dataWidth = 128
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),
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wdataFifoSize = 16,
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rdataFifoSize = 16
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)).doSimUntilVoid(seed = 42){dut =>
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val tester = new BmbMemoryTester(dut.io.input, dut.clockDomain, rspCounterTarget = 3000)
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dut.io.output.simSlave(tester.memory.memory, dut.clockDomain)
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}
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}
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@ -18,227 +18,6 @@ import vexriscv.plugin.{CsrPlugin, DBusCachedPlugin, DebugPlugin, IBusCachedPlug
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import scala.collection.mutable
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import scala.util.Random
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case class LiteDramNativeParameter(addressWidth : Int, dataWidth : Int)
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case class LiteDramNativeCmd(p : LiteDramNativeParameter) extends Bundle{
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val we = Bool()
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val addr = UInt(p.addressWidth bits)
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}
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case class LiteDramNativeWData(p : LiteDramNativeParameter) extends Bundle{
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val data = Bits(p.dataWidth bits)
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val we = Bits(p.dataWidth/8 bits)
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}
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case class LiteDramNativeRData(p : LiteDramNativeParameter) extends Bundle{
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val data = Bits(p.dataWidth bits)
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}
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case class LiteDramNative(p : LiteDramNativeParameter) extends Bundle with IMasterSlave {
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val cmd = Stream(LiteDramNativeCmd(p))
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val wdata = Stream(LiteDramNativeWData(p))
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val rdata = Stream(LiteDramNativeRData(p))
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override def asMaster(): Unit = {
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master(cmd, wdata)
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slave(rdata)
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}
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def fromBmb(bmb : Bmb, wdataFifoSize : Int, rdataFifoSize : Int) = {
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val bridge = BmbToLiteDram(
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bmbParameter = bmb.p,
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liteDramParameter = this.p,
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wdataFifoSize = wdataFifoSize,
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rdataFifoSize = rdataFifoSize
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)
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bridge.io.input << bmb
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bridge.io.output <> this
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bridge
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}
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def simSlave(ram : SparseMemory,cd : ClockDomain, bmb : Bmb = null): Unit ={
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import spinal.core.sim._
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def bus = this
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case class Cmd(address : Long, we : Boolean)
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case class WData(data : BigInt, we : Long)
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val cmdQueue = mutable.Queue[Cmd]()
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val wdataQueue = mutable.Queue[WData]()
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val rdataQueue = mutable.Queue[BigInt]()
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case class Ref(address : Long, data : BigInt, we : Long, time : Long)
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val ref = mutable.Queue[Ref]()
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if(bmb != null) StreamMonitor(bmb.cmd, cd){p =>
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if(bmb.cmd.opcode.toInt == 1) ref.enqueue(Ref(p.fragment.address.toLong, p.fragment.data.toBigInt, p.fragment.mask.toLong, simTime()))
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}
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var writeCmdCounter, writeDataCounter = 0
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StreamReadyRandomizer(bus.cmd, cd).factor = 0.5f
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StreamMonitor(bus.cmd, cd) { t =>
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cmdQueue.enqueue(Cmd(t.addr.toLong * (p.dataWidth/8) , t.we.toBoolean))
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if(t.we.toBoolean) writeCmdCounter += 1
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}
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StreamReadyRandomizer(bus.wdata, cd).factor = 0.5f
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StreamMonitor(bus.wdata, cd) { p =>
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writeDataCounter += 1
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// if(p.data.toBigInt == BigInt("00000002000000020000000200000002",16)){
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// println("ASD")
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// }
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wdataQueue.enqueue(WData(p.data.toBigInt, p.we.toLong))
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}
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// new SimStreamAssert(cmd,cd)
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// new SimStreamAssert(wdata,cd)
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// new SimStreamAssert(rdata,cd)
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cd.onSamplings{
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if(writeDataCounter-writeCmdCounter > 2){
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println("miaou")
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}
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if(cmdQueue.nonEmpty && Random.nextFloat() < 0.5){
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val cmd = cmdQueue.head
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if(cmd.we){
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if(wdataQueue.nonEmpty){
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// if(cmd.address == 0xc02ae850l) {
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// println(s"! $writeCmdCounter $writeDataCounter")
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// }
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cmdQueue.dequeue()
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val wdata = wdataQueue.dequeue()
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val raw = wdata.data.toByteArray
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val left = wdata.data.toByteArray.size-1
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if(bmb != null){
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assert(ref.nonEmpty)
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assert((ref.head.address & 0xFFFFFFF0l) == cmd.address)
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assert(ref.head.data == wdata.data)
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assert(ref.head.we == wdata.we)
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ref.dequeue()
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}
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// if(cmd.address == 0xc02ae850l) {
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// println(s"$cmd $wdata ${simTime()}")
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// }
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for(i <- 0 until p.dataWidth/8){
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if(((wdata.we >> i) & 1) != 0) {
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// if(cmd.address == 0xc02ae850l) {
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// println(s"W $i ${ if (left - i >= 0) raw(left - i) else 0}")
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// }
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ram.write(cmd.address + i, if (left - i >= 0) raw(left - i) else 0)
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}
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}
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}
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} else {
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cmdQueue.dequeue()
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val value = new Array[Byte](p.dataWidth/8+1)
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val left = value.size-1
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for(i <- 0 until p.dataWidth/8) {
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value(left-i) = ram.read(cmd.address+i)
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}
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rdataQueue.enqueue(BigInt(value))
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}
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}
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}
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StreamDriver(bus.rdata, cd){ p =>
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if(rdataQueue.isEmpty){
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false
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} else {
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p.data #= rdataQueue.dequeue()
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true
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}
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}
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}
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}
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case class BmbToLiteDram(bmbParameter : BmbParameter,
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liteDramParameter : LiteDramNativeParameter,
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wdataFifoSize : Int,
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rdataFifoSize : Int) extends Component{
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val io = new Bundle {
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val input = slave(Bmb(bmbParameter))
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val output = master(LiteDramNative(liteDramParameter))
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}
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val resized = io.input.resize(liteDramParameter.dataWidth)
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val unburstified = resized.unburstify()
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case class Context() extends Bundle {
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val context = Bits(unburstified.p.contextWidth bits)
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val source = UInt(unburstified.p.sourceWidth bits)
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val isWrite = Bool()
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}
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assert(isPow2(rdataFifoSize))
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val pendingRead = Reg(UInt(log2Up(rdataFifoSize) + 1 bits)) init(0)
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val halt = Bool()
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val (cmdFork, dataFork) = StreamFork2(unburstified.cmd.haltWhen(halt))
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val outputCmd = Stream(LiteDramNativeCmd(liteDramParameter))
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outputCmd.arbitrationFrom(cmdFork.haltWhen(pendingRead.msb))
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outputCmd.addr := (cmdFork.address >> log2Up(liteDramParameter.dataWidth/8)).resized
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outputCmd.we := cmdFork.isWrite
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io.output.cmd <-< outputCmd
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if(bmbParameter.canWrite) {
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val wData = Stream(LiteDramNativeWData(liteDramParameter))
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wData.arbitrationFrom(dataFork.throwWhen(dataFork.isRead))
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wData.data := dataFork.data
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wData.we := dataFork.mask
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io.output.wdata << wData.queueLowLatency(wdataFifoSize, latency = 1) //TODO queue low latency
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} else {
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dataFork.ready := True
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io.output.wdata.valid := False
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io.output.wdata.data.assignDontCare()
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io.output.wdata.we.assignDontCare()
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}
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val cmdContext = Stream(Context())
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cmdContext.valid := unburstified.cmd.fire
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cmdContext.context := unburstified.cmd.context
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cmdContext.source := unburstified.cmd.source
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cmdContext.isWrite := unburstified.cmd.isWrite
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halt := !cmdContext.ready
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val rspContext = cmdContext.queue(rdataFifoSize)
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val rdataFifo = io.output.rdata.queueLowLatency(rdataFifoSize, latency = 1)
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rdataFifo.ready := unburstified.rsp.fire && !rspContext.isWrite
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rspContext.ready := unburstified.rsp.fire
|
||||
unburstified.rsp.valid := rspContext.valid && (rspContext.isWrite || rdataFifo.valid)
|
||||
unburstified.rsp.setSuccess()
|
||||
unburstified.rsp.last := True
|
||||
unburstified.rsp.source := rspContext.source
|
||||
unburstified.rsp.context := rspContext.context
|
||||
unburstified.rsp.data := rdataFifo.data
|
||||
|
||||
|
||||
pendingRead := pendingRead + U(outputCmd.fire && !outputCmd.we) - U(rdataFifo.fire)
|
||||
}
|
||||
|
||||
object BmbToLiteDramTester extends App{
|
||||
import spinal.core.sim._
|
||||
SimConfig.withWave.compile(BmbToLiteDram(
|
||||
bmbParameter = BmbParameter(
|
||||
addressWidth = 20,
|
||||
dataWidth = 32,
|
||||
lengthWidth = 6,
|
||||
sourceWidth = 4,
|
||||
contextWidth = 16
|
||||
),
|
||||
liteDramParameter = LiteDramNativeParameter(
|
||||
addressWidth = 20,
|
||||
dataWidth = 128
|
||||
),
|
||||
wdataFifoSize = 16,
|
||||
rdataFifoSize = 16
|
||||
)).doSimUntilVoid(seed = 42){dut =>
|
||||
val tester = new BmbMemoryTester(dut.io.input, dut.clockDomain, rspCounterTarget = 3000)
|
||||
dut.io.output.simSlave(tester.memory.memory, dut.clockDomain)
|
||||
}
|
||||
}
|
||||
|
||||
case class VexRiscvLitexSmpClusterParameter( cluster : VexRiscvSmpClusterParameter,
|
||||
liteDram : LiteDramNativeParameter,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,262 @@
|
|||
package vexriscv.demo.smp
|
||||
|
||||
import spinal.core._
|
||||
import spinal.lib.bus.bmb._
|
||||
import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig, WishboneSlaveFactory}
|
||||
import spinal.lib.com.jtag.Jtag
|
||||
import spinal.lib._
|
||||
import spinal.lib.bus.bmb.sim.{BmbMemoryMultiPort, BmbMemoryTester}
|
||||
import spinal.lib.bus.misc.{AddressMapping, DefaultMapping, SizeMapping}
|
||||
import spinal.lib.eda.bench.Bench
|
||||
import spinal.lib.misc.Clint
|
||||
import spinal.lib.sim.{SimData, SparseMemory, StreamDriver, StreamMonitor, StreamReadyRandomizer}
|
||||
import vexriscv.demo.smp.VexRiscvLitexSmpDevClusterOpenSbi.{cpuCount, parameter}
|
||||
import vexriscv.demo.smp.VexRiscvSmpClusterGen.vexRiscvConfig
|
||||
import vexriscv.{VexRiscv, VexRiscvConfig}
|
||||
import vexriscv.plugin.{CsrPlugin, DBusCachedPlugin, DebugPlugin, IBusCachedPlugin}
|
||||
|
||||
import scala.collection.mutable
|
||||
import scala.util.Random
|
||||
|
||||
|
||||
case class VexRiscvLitexSmpDevClusterParameter( cluster : VexRiscvSmpClusterParameter,
|
||||
liteDram : LiteDramNativeParameter,
|
||||
liteDramMapping : AddressMapping)
|
||||
|
||||
//addAttribute("""mark_debug = "true"""")
|
||||
case class VexRiscvLitexSmpDevCluster(p : VexRiscvLitexSmpDevClusterParameter,
|
||||
debugClockDomain : ClockDomain) extends Component{
|
||||
|
||||
val peripheralWishboneConfig = WishboneConfig(
|
||||
addressWidth = 30,
|
||||
dataWidth = 32,
|
||||
selWidth = 4,
|
||||
useERR = true,
|
||||
useBTE = true,
|
||||
useCTI = true
|
||||
)
|
||||
|
||||
val cpuCount = p.cluster.cpuConfigs.size
|
||||
|
||||
val io = new Bundle {
|
||||
val dMem = Vec(master(LiteDramNative(p.liteDram)), cpuCount)
|
||||
val iMem = Vec(master(LiteDramNative(p.liteDram)), cpuCount)
|
||||
val peripheral = master(Wishbone(peripheralWishboneConfig))
|
||||
val clint = slave(Wishbone(Clint.getWisboneConfig()))
|
||||
val externalInterrupts = in Bits(p.cluster.cpuConfigs.size bits)
|
||||
val externalSupervisorInterrupts = in Bits(p.cluster.cpuConfigs.size bits)
|
||||
val jtag = slave(Jtag())
|
||||
val debugReset = out Bool()
|
||||
}
|
||||
val clint = Clint(cpuCount)
|
||||
clint.driveFrom(WishboneSlaveFactory(io.clint))
|
||||
|
||||
val cluster = VexRiscvSmpCluster(p.cluster, debugClockDomain)
|
||||
cluster.io.externalInterrupts <> io.externalInterrupts
|
||||
cluster.io.externalSupervisorInterrupts <> io.externalSupervisorInterrupts
|
||||
cluster.io.jtag <> io.jtag
|
||||
cluster.io.debugReset <> io.debugReset
|
||||
cluster.io.timerInterrupts <> B(clint.harts.map(_.timerInterrupt))
|
||||
cluster.io.softwareInterrupts <> B(clint.harts.map(_.softwareInterrupt))
|
||||
|
||||
val dBusDecoder = BmbDecoderOutOfOrder(
|
||||
p = cluster.io.dMem.p,
|
||||
mappings = Seq(DefaultMapping, p.liteDramMapping),
|
||||
capabilities = Seq(cluster.io.dMem.p, cluster.io.dMem.p),
|
||||
pendingRspTransactionMax = 32
|
||||
)
|
||||
// val dBusDecoder = BmbDecoderOut(
|
||||
// p = cluster.io.dMem.p,
|
||||
// mappings = Seq(DefaultMapping, p.liteDramMapping),
|
||||
// capabilities = Seq(cluster.io.dMem.p, cluster.io.dMem.p),
|
||||
// pendingMax = 31
|
||||
// )
|
||||
dBusDecoder.io.input << cluster.io.dMem.pipelined(cmdValid = true, cmdReady = true, rspValid = true)
|
||||
|
||||
|
||||
val perIBus = for(id <- 0 until cpuCount) yield new Area{
|
||||
val decoder = BmbDecoder(
|
||||
p = cluster.io.iMems(id).p,
|
||||
mappings = Seq(DefaultMapping, p.liteDramMapping),
|
||||
capabilities = Seq(cluster.io.iMems(id).p,cluster.io.iMems(id).p),
|
||||
pendingMax = 15
|
||||
)
|
||||
|
||||
decoder.io.input << cluster.io.iMems(id)
|
||||
io.iMem(id).fromBmb(decoder.io.outputs(1), wdataFifoSize = 0, rdataFifoSize = 32)
|
||||
val toPeripheral = decoder.io.outputs(0).resize(dataWidth = 32)
|
||||
}
|
||||
|
||||
val dBusDecoderToPeripheral = dBusDecoder.io.outputs(0).resize(dataWidth = 32).pipelined(cmdHalfRate = true, rspValid = true)
|
||||
|
||||
val peripheralAccessLength = Math.max(perIBus(0).toPeripheral.p.lengthWidth, dBusDecoder.io.outputs(0).p.lengthWidth)
|
||||
val peripheralArbiter = BmbArbiter(
|
||||
p = dBusDecoder.io.outputs(0).p.copy(
|
||||
sourceWidth = List(perIBus(0).toPeripheral, dBusDecoderToPeripheral).map(_.p.sourceWidth).max + log2Up(cpuCount + 1),
|
||||
contextWidth = List(perIBus(0).toPeripheral, dBusDecoderToPeripheral).map(_.p.contextWidth).max,
|
||||
lengthWidth = peripheralAccessLength,
|
||||
dataWidth = 32
|
||||
),
|
||||
portCount = cpuCount+1,
|
||||
lowerFirstPriority = true
|
||||
)
|
||||
|
||||
for(id <- 0 until cpuCount){
|
||||
peripheralArbiter.io.inputs(id) << perIBus(id).toPeripheral
|
||||
}
|
||||
peripheralArbiter.io.inputs(cpuCount) << dBusDecoderToPeripheral
|
||||
|
||||
val peripheralWishbone = peripheralArbiter.io.output.pipelined(cmdValid = true).toWishbone()
|
||||
io.peripheral << peripheralWishbone
|
||||
|
||||
|
||||
val dBusDemux = BmbSourceDecoder(dBusDecoder.io.outputs(1).p)
|
||||
dBusDemux.io.input << dBusDecoder.io.outputs(1)
|
||||
val dMemBridge = for(id <- 0 until cpuCount) yield {
|
||||
io.dMem(id).fromBmb(dBusDemux.io.outputs(id), wdataFifoSize = 32, rdataFifoSize = 32)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
object VexRiscvLitexSmpDevClusterGen extends App {
|
||||
for(cpuCount <- List(1,2,4,8)) {
|
||||
def parameter = VexRiscvLitexSmpDevClusterParameter(
|
||||
cluster = VexRiscvSmpClusterParameter(
|
||||
cpuConfigs = List.tabulate(cpuCount) { hartId =>
|
||||
vexRiscvConfig(
|
||||
hartId = hartId,
|
||||
ioRange = address => address.msb,
|
||||
resetVector = 0
|
||||
)
|
||||
}
|
||||
),
|
||||
liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
|
||||
liteDramMapping = SizeMapping(0x40000000l, 0x40000000l)
|
||||
)
|
||||
|
||||
def dutGen = {
|
||||
val toplevel = VexRiscvLitexSmpDevCluster(
|
||||
p = parameter,
|
||||
debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
|
||||
)
|
||||
toplevel
|
||||
}
|
||||
|
||||
val genConfig = SpinalConfig().addStandardMemBlackboxing(blackboxByteEnables)
|
||||
// genConfig.generateVerilog(Bench.compressIo(dutGen))
|
||||
genConfig.generateVerilog(dutGen.setDefinitionName(s"VexRiscvLitexSmpDevCluster_${cpuCount}c"))
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
object VexRiscvLitexSmpDevClusterOpenSbi extends App{
|
||||
import spinal.core.sim._
|
||||
|
||||
val simConfig = SimConfig
|
||||
simConfig.withWave
|
||||
simConfig.allOptimisation
|
||||
|
||||
val cpuCount = 4
|
||||
|
||||
def parameter = VexRiscvLitexSmpDevClusterParameter(
|
||||
cluster = VexRiscvSmpClusterParameter(
|
||||
cpuConfigs = List.tabulate(cpuCount) { hartId =>
|
||||
vexRiscvConfig(
|
||||
hartId = hartId,
|
||||
ioRange = address => address(31 downto 28) === 0xF,
|
||||
resetVector = 0x80000000l
|
||||
)
|
||||
}
|
||||
),
|
||||
liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
|
||||
liteDramMapping = SizeMapping(0x80000000l, 0x70000000l)
|
||||
)
|
||||
|
||||
def dutGen = {
|
||||
val top = VexRiscvLitexSmpDevCluster(
|
||||
p = parameter,
|
||||
debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
|
||||
)
|
||||
top.rework{
|
||||
top.io.clint.setAsDirectionLess.allowDirectionLessIo
|
||||
top.io.peripheral.setAsDirectionLess.allowDirectionLessIo.simPublic()
|
||||
|
||||
val hit = (top.io.peripheral.ADR <<2 >= 0xF0010000l && top.io.peripheral.ADR<<2 < 0xF0020000l)
|
||||
top.io.clint.CYC := top.io.peripheral.CYC && hit
|
||||
top.io.clint.STB := top.io.peripheral.STB
|
||||
top.io.clint.WE := top.io.peripheral.WE
|
||||
top.io.clint.ADR := top.io.peripheral.ADR.resized
|
||||
top.io.clint.DAT_MOSI := top.io.peripheral.DAT_MOSI
|
||||
top.io.peripheral.DAT_MISO := top.io.clint.DAT_MISO
|
||||
top.io.peripheral.ACK := top.io.peripheral.CYC && (!hit || top.io.clint.ACK)
|
||||
top.io.peripheral.ERR := False
|
||||
|
||||
// top.dMemBridge.unburstified.cmd.simPublic()
|
||||
}
|
||||
top
|
||||
}
|
||||
simConfig.compile(dutGen).doSimUntilVoid(seed = 42){dut =>
|
||||
dut.clockDomain.forkStimulus(10)
|
||||
fork {
|
||||
dut.debugClockDomain.resetSim #= false
|
||||
sleep (0)
|
||||
dut.debugClockDomain.resetSim #= true
|
||||
sleep (10)
|
||||
dut.debugClockDomain.resetSim #= false
|
||||
}
|
||||
|
||||
|
||||
val ram = SparseMemory()
|
||||
ram.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin")
|
||||
ram.loadBin(0xC0000000l, "../buildroot/output/images/Image")
|
||||
ram.loadBin(0xC1000000l, "../buildroot/output/images/dtb")
|
||||
ram.loadBin(0xC2000000l, "../buildroot/output/images/rootfs.cpio")
|
||||
|
||||
for(id <- 0 until cpuCount) {
|
||||
dut.io.iMem(id).simSlave(ram, dut.clockDomain)
|
||||
dut.io.dMem(id).simSlave(ram, dut.clockDomain)
|
||||
}
|
||||
|
||||
dut.io.externalInterrupts #= 0
|
||||
dut.io.externalSupervisorInterrupts #= 0
|
||||
|
||||
dut.clockDomain.onSamplings{
|
||||
if(dut.io.peripheral.CYC.toBoolean){
|
||||
(dut.io.peripheral.ADR.toLong << 2) match {
|
||||
case 0xF0000000l => print(dut.io.peripheral.DAT_MOSI.toLong.toChar)
|
||||
case 0xF0000004l => dut.io.peripheral.DAT_MISO #= (if(System.in.available() != 0) System.in.read() else 0xFFFFFFFFl)
|
||||
case _ =>
|
||||
}
|
||||
// println(f"${dut.io.peripheral.ADR.toLong}%x")
|
||||
}
|
||||
}
|
||||
|
||||
// fork{
|
||||
// disableSimWave()
|
||||
// val atMs = 3790
|
||||
// val durationMs = 5
|
||||
// sleep(atMs*1000000l)
|
||||
// enableSimWave()
|
||||
// println("** enableSimWave **")
|
||||
// sleep(durationMs*1000000l)
|
||||
// println("** disableSimWave **")
|
||||
// while(true) {
|
||||
// disableSimWave()
|
||||
// sleep(100000 * 10)
|
||||
// enableSimWave()
|
||||
// sleep( 100 * 10)
|
||||
// }
|
||||
// // simSuccess()
|
||||
// }
|
||||
|
||||
fork{
|
||||
while(true) {
|
||||
disableSimWave()
|
||||
sleep(100000 * 10)
|
||||
enableSimWave()
|
||||
sleep( 100 * 10)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue