Fix BRANCH_TARGET with RVC patch
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41008551c1
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@ -421,18 +421,15 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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}
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}
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def stage1ToInjectorPipe[T <: Data](input : T): (T,T) ={
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def stage1ToInjectorPipe[T <: Data](input : T): (T, T, T) ={
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val iBusRspContext = iBusRsp.stages.drop(1).dropRight(1).foldLeft(input)((data,stage) => RegNextWhen(data, stage.output.ready))
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// val decompressorContext = ifGen(compressedGen)(new Area{
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// val lastContext = RegNextWhen(iBusRspContext, decompressor.input.fire)
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// val output = decompressor.bufferValid ? lastContext | iBusRspContext
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// })
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val decompressorContext = cloneOf(input)
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decompressorContext := iBusRspContext
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val injectorContext = Delay(if(compressedGen) decompressorContext else iBusRspContext, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready)
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val iBusRspContextOutput = cloneOf(input)
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iBusRspContextOutput := iBusRspContext
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val injectorContext = Delay(iBusRspContextOutput, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready)
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val injectorContextWire = cloneOf(input) //Allow combinatorial override
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injectorContextWire := injectorContext
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(ifGen(compressedGen)(decompressorContext), injectorContextWire)
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(iBusRspContext, iBusRspContextOutput, injectorContextWire)
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}
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val predictor = prediction match {
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@ -458,7 +455,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.stages(0).output.ready || fetcherflushIt)
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object PREDICTION_CONTEXT extends Stageable(DynamicContext())
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decode.insert(PREDICTION_CONTEXT) := stage1ToInjectorPipe(fetchContext)._2
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decode.insert(PREDICTION_CONTEXT) := stage1ToInjectorPipe(fetchContext)._3
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val decodeContextPrediction = decode.input(PREDICTION_CONTEXT).line.history.msb
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val branchStage = decodePrediction.stage
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@ -534,21 +531,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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fetchContext.hit := hit
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fetchContext.line := line
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val (decompressorContext, injectorContext) = stage1ToInjectorPipe(fetchContext)
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if(compressedGen) {
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//prediction hit on the right instruction into words
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decompressorContext.hit clearWhen(decompressorContext.line.last2Bytes && (decompressor.bufferValid || (decompressor.isRvc && !decompressor.throw2Bytes)))
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decodePc.predictionPcLoad.valid := injectorContext.line.branchWish.msb && injectorContext.hit && !injectorContext.hazard && injector.decodeInput.fire
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decodePc.predictionPcLoad.payload := injectorContext.line.target
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//Clean the RVC buffer when a prediction was made
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when(decompressorContext.line.branchWish.msb && decompressorContext.hit && !decompressorContext.hazard && decompressor.output.fire){
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decompressor.bufferValid := False
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decompressor.throw2BytesReg := False
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decompressor.input.ready := True //Drop the remaining byte if any
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}
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}
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val (decompressorContext, decompressorContextOutput, injectorContext) = stage1ToInjectorPipe(fetchContext)
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object PREDICTION_CONTEXT extends Stageable(PredictionResult())
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pipeline.decode.insert(PREDICTION_CONTEXT) := injectorContext
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@ -580,7 +563,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring)
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val predictionFailure = ifGen(compressedGen)(new Area{
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val compressor = compressedGen generate new Area{
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val predictionBranch = decompressorContext.hit && !decompressorContext.hazard && decompressorContext.line.branchWish(1)
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val unalignedWordIssue = iBusRsp.output.valid && predictionBranch && decompressor.throw2Bytes && !decompressor.isInputHighRvc
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@ -591,7 +574,20 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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iBusRsp.redoFetch := True
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}
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})
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//Do not trigger prediction hit when it is one for the upper RVC word and we aren't there yet
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decompressorContextOutput.hit clearWhen(decompressorContext.line.last2Bytes && !decompressor.throw2Bytes)
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decodePc.predictionPcLoad.valid := injectorContext.line.branchWish.msb && injectorContext.hit && !injectorContext.hazard && injector.decodeInput.fire
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decodePc.predictionPcLoad.payload := injectorContext.line.target
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//Clean the RVC buffer when a prediction was made
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when(decompressorContext.line.branchWish.msb && decompressorContextOutput.hit && !decompressorContext.hazard && decompressor.output.fire){
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decompressor.bufferValid := False
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decompressor.throw2BytesReg := False
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decompressor.input.ready := True //Drop the remaining byte if any
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}
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}
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}
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}
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@ -620,7 +620,7 @@ class TestIndividualFeatures extends FunSuite {
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test(prefix + name + "_test") {
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println("START TEST " + prefix + name)
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val debug = true
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val stdCmd = (s"make clean run WITH_USER_IO=no REDO=10 TRACE=${if(debug) "yes" else "no"} TRACE_START=9999924910246l STOP_ON_ERROR=no FLOW_INFO=no STOP_ON_ERROR=no DHRYSTONE=yes COREMARK=${sys.env.getOrElse("VEXRISCV_REGRESSION_COREMARK", "yes")} THREAD_COUNT=${sys.env.getOrElse("VEXRISCV_REGRESSION_THREAD_COUNT", 1)} ") + s" SEED=${testSeed} "
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val stdCmd = (s"make clean run WITH_USER_IO=no REDO=10 TRACE=${if(debug) "yes" else "no"} TRACE_START=9999924910246l FLOW_INFO=no STOP_ON_ERROR=no DHRYSTONE=yes COREMARK=${sys.env.getOrElse("VEXRISCV_REGRESSION_COREMARK", "yes")} THREAD_COUNT=${sys.env.getOrElse("VEXRISCV_REGRESSION_THREAD_COUNT", 1)} ") + s" SEED=${testSeed} "
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val testCmd = stdCmd + (positionsToApply).map(_.testParam).mkString(" ")
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println(testCmd)
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val str = doCmd(testCmd)
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@ -633,8 +633,8 @@ class TestIndividualFeatures extends FunSuite {
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//
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// val testId = Some(mutable.HashSet(3,4,9,11,13,16,18,19,20,21))
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// val testId = Some(mutable.HashSet(11))
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// val testId = Some(mutable.HashSet(4, 11))
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// val seed = 6592877339343561798l
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// val testId = Some(mutable.HashSet(6))
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// val seed = 9095713085965080531l
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val rand = new Random(seed)
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