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VexRiscv
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remove rspStageGen

This commit is contained in:
Dolu1990 2018-05-14 09:21:28 +02:00
parent 7b37669a0f
commit 610bd01f3b
3 changed files with 15 additions and 16 deletions
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6
src/main/scala/vexriscv/plugin/Fetcher.scala
View File

@ -15,7 +15,6 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
val decodePcGen : Boolean,
val compressedGen : Boolean,
val cmdToRspStageCount : Int,
val rspStageGen : Boolean,
val injectorReadyCutGen : Boolean,
val relaxedPcCalculation : Boolean,
val prediction : BranchPrediction,
@ -212,9 +211,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
// ...
val readyForError = True
val outputBeforeStage = Stream(FetchRsp())
val output = if(rspStageGen) outputBeforeStage.m2sPipeWithFlush(flush, collapsBubble = false) else outputBeforeStage
if(rspStageGen) readyForError.clearWhen(output.valid)
val output = Stream(FetchRsp())
incomingInstruction setWhen(inputPipeline.map(_.valid).orR)
}
@ -274,7 +271,6 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
decodeNextPc := decodePc.pcReg
} else {
val lastStageStream = if (injectorStage) inputBeforeHalt
else if (rspStageGen) iBusRsp.outputBeforeStage
else if (cmdToRspStageCount > 1) iBusRsp.inputPipeline(cmdToRspStageCount - 2)
else throw new Exception("Fetch should at least have two stages")

7
src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
View File

@ -16,7 +16,6 @@ class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConf
decodePcGen = false,
compressedGen = false,
cmdToRspStageCount = 1,
rspStageGen = false,
injectorReadyCutGen = false,
relaxedPcCalculation = false,
prediction = NONE,
@ -148,9 +147,9 @@ class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConf
}
iBusRsp.outputBeforeStage.arbitrationFrom(iBusRsp.inputPipeline(0).haltWhen(issueDetected))
iBusRsp.outputBeforeStage.rsp.inst := cache.io.cpu.fetch.data
iBusRsp.outputBeforeStage.pc := iBusRsp.inputPipeline(0).payload
iBusRsp.output.arbitrationFrom(iBusRsp.inputPipeline(0).haltWhen(issueDetected))
iBusRsp.output.rsp.inst := cache.io.cpu.fetch.data
iBusRsp.output.pc := iBusRsp.inputPipeline(0).payload
// if (dataOnDecode) {

18
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View File

@ -105,18 +105,22 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste
class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean, pendingMax : Int = 7) extends IBusFetcherImpl(
class IBusSimplePlugin(interfaceKeepData : Boolean,
catchAccessFault : Boolean,
// resetVector : BigInt,
// keepPcPlus4 : Boolean,
// decodePcGen : Boolean,
pendingMax : Int = 7) extends IBusFetcherImpl(
catchAccessFault = catchAccessFault,
resetVector = BigInt(0x80000000l),
keepPcPlus4 = false,
decodePcGen = true,
compressedGen = true,
decodePcGen = false,
compressedGen = false,
cmdToRspStageCount = 1,
rspStageGen = false,
injectorReadyCutGen = false,
relaxedPcCalculation = false,
relaxedPcCalculation = true,
prediction = NONE,
catchAddressMisaligned = true,
catchAddressMisaligned = false,
injectorStage = true){
var iBus : IBusSimpleBus = null
var decodeExceptionPort : Flow[ExceptionCause] = null
@ -177,7 +181,7 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
var issueDetected = False
val join = StreamJoin(Seq(inputPipeline.last, rspBuffer.io.pop), fetchRsp)
inputPipeline.last.ready setWhen(!inputPipeline.last.valid)
outputBeforeStage << join.haltWhen(issueDetected)
output << join.haltWhen(issueDetected)
if(catchAccessFault){
decodeExceptionPort.valid := False