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Add smallAndProductive

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This commit is contained in:
Charles Papon 2017-07-17 15:25:56 +02:00
parent 431750cac3
commit 617861ee6c
4 changed files with 91 additions and 42 deletions
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60
src/main/scala/VexRiscv/demo/GenSmallAndPerformant.scala Normal file
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@ -0,0 +1,60 @@
package VexRiscv.demo
import VexRiscv.Plugin._
import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig}
import spinal.core._
/**
* Created by spinalvm on 15.06.17.
*/
object GenSmallAndProductive extends App{
def cpu() = new VexRiscv(
config = VexRiscvConfig(
plugins = List(
new PcManagerSimplePlugin(
resetVector = 0x00000000l,
fastPcCalculation = true
),
new IBusSimplePlugin(
interfaceKeepData = false,
catchAccessFault = false
),
new DBusSimplePlugin(
catchAddressMisaligned = false,
catchAccessFault = false
),
new CsrPlugin(CsrPluginConfig.smallest),
new DecoderSimplePlugin(
catchIllegalInstruction = false
),
new RegFilePlugin(
regFileReadyKind = Plugin.SYNC,
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
separatedAddSub = false,
executeInsertion = true
),
new LightShifterPlugin,
new HazardSimplePlugin(
bypassExecute = true,
bypassMemory = true,
bypassWriteBack = true,
bypassWriteBackBuffer = true,
pessimisticUseSrc = false,
pessimisticWriteRegFile = false,
pessimisticAddressMatch = false
),
new BranchPlugin(
earlyBranch = false,
catchAddressMisaligned = false,
prediction = NONE
),
new YamlPlugin("cpu0.yaml")
)
)
)
SpinalVerilog(cpu())
}

9
src/main/scala/VexRiscv/demo/SynthesisBench.scala
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@ -20,6 +20,13 @@ object SynthesisBench {
SpinalVerilog(GenSmallest.cpu().setDefinitionName(getRtlPath().split("\\.").head))
}
val smallAndProductive = new Rtl {
override def getName(): String = "VexRiscv small and productive"
override def getRtlPath(): String = "VexRiscvSmallAndProductive.v"
SpinalVerilog(GenSmallAndProductive.cpu().setDefinitionName(getRtlPath().split("\\.").head))
}
val fullNoMmu = new Rtl {
override def getName(): String = "VexRiscv full no MMU"
override def getRtlPath(): String = "VexRiscvFullNoMmu.v"
@ -32,7 +39,7 @@ object SynthesisBench {
SpinalVerilog(GenFull.cpu().setDefinitionName(getRtlPath().split("\\.").head))
}
val rtls = List(smallestNoCsr, smallest, fullNoMmu, full)
val rtls = List(smallestNoCsr, smallest, smallAndProductive, fullNoMmu, full)
val targets = XilinxStdTargets(
vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin"

63
src/test/cpp/regression/fail.gtkw
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@ -1,55 +1,36 @@
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Sat Jun 24 10:59:33 2017
[*] Mon Jul 17 12:56:44 2017
[*]
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/regression/debugPluginExternal.vcd"
[dumpfile_mtime] "Sat Jun 24 10:59:20 2017"
[dumpfile_size] 147859982
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/regression/dhrystoneO3M.vcd"
[dumpfile_mtime] "Mon Jul 17 09:34:42 2017"
[dumpfile_size] 711052321
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/regression/fail.gtkw"
[timestart] 0
[size] 1728 935
[pos] -775 -1
*-16.000000 221100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 100656
[size] 1776 953
[pos] -775 -353
*-9.000000 101506 62802 257426 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.VexRiscv.
[sst_width] 260
[signals_width] 486
[sst_width] 242
[signals_width] 409
[sst_expanded] 1
[sst_vpaned_height] 273
[sst_vpaned_height] 279
@22
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_address[31:0]
TOP.VexRiscv.CsrPlugin_mcycle[63:0]
TOP.VexRiscv.dBus_cmd_payload_address[31:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_clean
TOP.VexRiscv.dBus_cmd_payload_wr
TOP.VexRiscv.dBus_cmd_ready
TOP.VexRiscv.dBus_cmd_valid
@22
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_data[31:0]
TOP.VexRiscv.CsrPlugin_minstret[63:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_forceUncachedAccess
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_invalidate
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_kind[0]
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_size[1:0]
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_way
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_wr
TOP.VexRiscv.DebugPlugin_haltIt
TOP.VexRiscv.DebugPlugin_haltedByBreak
TOP.VexRiscv.DebugPlugin_stepIt
@22
TOP.VexRiscv.execute_PC[31:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_isValid
@22
TOP.VexRiscv.RegFilePlugin_regFile(15)[31:0]
TOP.VexRiscv.RegFilePlugin_regFile(2)[31:0]
TOP.VexRiscv.DebugPlugin_busReadDataReg[31:0]
TOP.debug_bus_cmd_payload_address[7:0]
TOP.debug_bus_cmd_payload_data[31:0]
@28
TOP.debug_bus_cmd_payload_wr
TOP.VexRiscv.writeBack_IS_MUL
TOP.VexRiscv.writeBack_arbitration_isFiring
TOP.VexRiscv.memory_IS_DIV
TOP.VexRiscv.memory_arbitration_isFiring
@29
TOP.debug_bus_cmd_valid
TOP.debug_bus_cmd_ready
@23
TOP.debug_bus_rsp_data[31:0]
@22
TOP.VexRiscv.RegFilePlugin_regFile(2)[31:0]
TOP.VexRiscv.decode_arbitration_haltIt
[pattern_trace] 1
[pattern_trace] 0

1
src/test/cpp/regression/main.cpp
View file

@ -1233,6 +1233,7 @@ int main(int argc, char **argv, char **env) {
printf("BOOT\n");
timespec startedAt = timer_start();
Dhrystone("dhrystoneO3","dhrystoneO3",false,false).run(1.5e6);
for(int idx = 0;idx < 1;idx++){
#ifndef REF