Port to iCE40HX8K-EVB

scripts/Murax_iCE40HX8K-EVB/makefile

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+
+
+VERILOG = ../../Murax.v toplevel.v toplevel_pll.v
+
+generate :
+	(cd ../..; sbt "run-main vexriscv.demo.MuraxWithRamInit")
+
+../../Murax.v :
+	(cd ../..; sbt "run-main vexriscv.demo.MuraxWithRamInit")
+
+bin/toplevel.blif : ${VERILOG}
+	mkdir -p bin
+	yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG}
+
+bin/toplevel.asc : toplevel.pcf bin/toplevel.blif
+	arachne-pnr -p toplevel.pcf -d 8k --max-passes 600 -P ct256 bin/toplevel.blif -o bin/toplevel.asc
+
+bin/toplevel.bin : bin/toplevel.asc
+	icepack bin/toplevel.asc bin/toplevel.bin
+
+compile : bin/toplevel.bin
+
+time: bin/toplevel.bin
+	icetime -tmd hx8k bin/toplevel.asc
+
+prog : bin/toplevel.bin
+	iceprogduino bin/toplevel.bin
+
+sudo-prog : bin/toplevel.bin
+	sudo iceprogduino bin/toplevel.bin
+
+clean :
+	rm -rf bin

scripts/Murax_iCE40HX8K-EVB/toplevel.pcf

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+set_io CLK J3
+set_io BUT1 K11
+set_io BUT2 P13
+set_io LED1 M12
+set_io LED2 R16

scripts/Murax_iCE40HX8K-EVB/toplevel.v

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+`timescale 1ns / 1ps
+
+module toplevel(
+    input   CLK,
+    input   BUT1,
+    input   BUT2,
+    output  LED1,
+    output  LED2
+  );
+
+  assign LED1 = io_gpioA_write[0];
+  assign LED2 = io_gpioA_write[7];
+
+  wire [31:0] io_gpioA_read;
+  wire [31:0] io_gpioA_write;
+  wire [31:0] io_gpioA_writeEnable;
+  wire io_mainClk;
+
+  // Use PLL to downclock external clock.
+  toplevel_pll toplevel_pll_inst(.REFERENCECLK(CLK),
+                                 .PLLOUTCORE(io_mainClk),
+                                 .PLLOUTGLOBAL(),
+                                 .RESET(1'b1));
+
+  Murax murax ( 
+    .io_asyncReset(1'b0),
+    .io_mainClk (io_mainClk),
+    .io_jtag_tck(1'b0),
+    .io_jtag_tdi(1'b0),
+    .io_jtag_tdo(),
+    .io_jtag_tms(1'b0),
+    .io_gpioA_read       (io_gpioA_read),
+    .io_gpioA_write      (io_gpioA_write),
+    .io_gpioA_writeEnable(io_gpioA_writeEnable),
+    .io_uart_txd(),
+    .io_uart_rxd(0'b0)
+  );
+
+endmodule

scripts/Murax_iCE40HX8K-EVB/toplevel_pll.v

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+module toplevel_pll(REFERENCECLK,
+                    PLLOUTCORE,
+                    PLLOUTGLOBAL,
+                    RESET);
+
+input REFERENCECLK;
+input RESET;    /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ 
+output PLLOUTCORE;
+output PLLOUTGLOBAL;
+
+SB_PLL40_CORE toplevel_pll_inst(.REFERENCECLK(REFERENCECLK),
+                                .PLLOUTCORE(PLLOUTCORE),
+                                .PLLOUTGLOBAL(PLLOUTGLOBAL),
+                                .EXTFEEDBACK(),
+                                .DYNAMICDELAY(),
+                                .RESETB(RESET),
+                                .BYPASS(1'b0),
+                                .LATCHINPUTVALUE(),
+                                .LOCK(),
+                                .SDI(),
+                                .SDO(),
+                                .SCLK());
+
+//\\ Fin=100, Fout=12;
+defparam toplevel_pll_inst.DIVR = 4'b0010;
+defparam toplevel_pll_inst.DIVF = 7'b0010110;
+defparam toplevel_pll_inst.DIVQ = 3'b110;
+defparam toplevel_pll_inst.FILTER_RANGE = 3'b011;
+defparam toplevel_pll_inst.FEEDBACK_PATH = "SIMPLE";
+defparam toplevel_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
+defparam toplevel_pll_inst.FDA_FEEDBACK = 4'b0000;
+defparam toplevel_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
+defparam toplevel_pll_inst.FDA_RELATIVE = 4'b0000;
+defparam toplevel_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
+defparam toplevel_pll_inst.PLLOUT_SELECT = "GENCLK";
+defparam toplevel_pll_inst.ENABLE_ICEGATE = 1'b0;
+
+endmodule