xip refractoring
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@ -119,7 +119,12 @@ make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRE
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rm -rf cpio
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mkdir cpio
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cd cpio
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cpio -idv < ../rootfs.cpio
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sudo cpio -i < ../rootfs.cpio
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cd ..
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rm rootfs.cpio
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cd cpio
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sudo find | sudo cpio -H newc -o > ../rootfs.cpio
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cd ..
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make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes MMU=yes CSR=yes COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=10 TRACE=no COREMARK=yes LINUX_REGRESSION=yes RUN_HEX=~/pro/riscv/zephyr/samples/synchronization/build/zephyr/zephyr.hex
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@ -65,7 +65,7 @@ object MuraxConfig{
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SpiXdrMasterCtrl.Parameters(8, 12, SpiXdrParameter(2, 2, 1)).addFullDuplex(0,1,false),
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cmdFifoDepth = 32,
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rspFifoDepth = 32,
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xip = SpiXdrMasterCtrl.XipBusParameters(addressWidth = 24, dataWidth = 32)
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xip = SpiXdrMasterCtrl.XipBusParameters(addressWidth = 24, lengthWidth = 2)
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)),
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hardwareBreakpointCount = if(withXip) 3 else 0,
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cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel
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@ -298,13 +298,7 @@ case class Murax(config : MuraxConfig) extends Component{
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val accessBus = new PipelinedMemoryBus(PipelinedMemoryBusConfig(24,32))
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mainBusMapping += accessBus -> (0xE0000000l, 16 MB)
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ctrl.io.xip.cmd.valid <> (accessBus.cmd.valid && !accessBus.cmd.write)
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ctrl.io.xip.cmd.ready <> accessBus.cmd.ready
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ctrl.io.xip.cmd.payload <> accessBus.cmd.address
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ctrl.io.xip.rsp.valid <> accessBus.rsp.valid
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ctrl.io.xip.rsp.payload <> accessBus.rsp.data
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ctrl.io.xip.fromPipelinedMemoryBus() << accessBus
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val bootloader = Apb3Rom("src/main/c/murax/xipBootloader/crt.bin")
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apbMapping += bootloader.io.apb -> (0x1E000, 4 kB)
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})
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