fpu now track commits using a counter per pipeline per port
This commit is contained in:
Dolu1990
parent
81c193af1f
commit
636d53cf63
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@ -26,7 +26,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val exponentF64Infinity = exponentOne+1023+1
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val lockIdType = HardType(UInt(log2Up(p.rfLockCount) bits))
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def whenDouble(format : FpuFormat.C)(yes : => Unit)(no : => Unit): Unit ={
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if(p.withDouble) when(format === FpuFormat.DOUBLE) { yes } otherwise{ no }
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@ -51,7 +50,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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case class RfReadOutput() extends Bundle{
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val source = Source()
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val opcode = p.Opcode()
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val lockId = lockIdType()
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val rs1, rs2, rs3 = p.internalFloating()
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val rd = p.rfAddress()
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val arg = p.Arg()
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@ -64,7 +62,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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case class LoadInput() extends Bundle{
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val source = Source()
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val rd = p.rfAddress()
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val lockId = lockIdType()
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val i2f = Bool()
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val arg = Bits(2 bits)
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val roundMode = FpuRoundMode()
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@ -75,7 +72,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val source = Source()
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val opcode = p.Opcode()
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val rs1, rs2 = p.internalFloating()
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val lockId = lockIdType()
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val rd = p.rfAddress()
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val value = Bits(32 bits)
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val arg = Bits(2 bits)
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@ -88,7 +84,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val source = Source()
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val rs1, rs2, rs3 = p.internalFloating()
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val rd = p.rfAddress()
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val lockId = lockIdType()
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val add = Bool()
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val divSqrt = Bool()
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val msb1, msb2 = Bool() //allow usage of msb bits of mul
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@ -101,7 +96,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val source = Source()
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val rs1, rs2 = p.internalFloating()
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val rd = p.rfAddress()
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val lockId = lockIdType()
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val div = Bool()
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val roundMode = FpuRoundMode()
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val format = p.withDouble generate FpuFormat()
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@ -111,7 +105,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val source = Source()
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val rs1, rs2 = p.internalFloating()
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val rd = p.rfAddress()
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val lockId = lockIdType()
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val roundMode = FpuRoundMode()
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val format = p.withDouble generate FpuFormat()
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}
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@ -121,7 +114,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val source = Source()
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val rs1 = p.internalFloating()
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val rd = p.rfAddress()
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val lockId = lockIdType()
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val roundMode = FpuRoundMode()
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val format = p.withDouble generate FpuFormat()
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}
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@ -131,15 +123,14 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val source = Source()
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val rs1, rs2 = p.internalFloating()
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val rd = p.rfAddress()
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val lockId = lockIdType()
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val roundMode = FpuRoundMode()
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val format = p.withDouble generate FpuFormat()
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val needCommit = Bool()
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}
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class MergeInput() extends Bundle{
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val source = Source()
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val lockId = lockIdType()
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val rd = p.rfAddress()
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val value = p.writeFloating()
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val scrap = Bool()
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@ -151,7 +142,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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case class RoundOutput() extends Bundle{
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val source = Source()
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val lockId = lockIdType()
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val rd = p.rfAddress()
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val value = p.internalFloating()
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val format = p.withDouble generate FpuFormat()
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@ -165,16 +155,28 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val boxed = p.withDouble generate Bool()
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}
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val ram = Mem(Entry(), 32*portCount)
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val lock = for(i <- 0 until p.rfLockCount) yield new Area{
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val valid = RegInit(False)
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val source = Reg(Source())
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val address = Reg(p.rfAddress)
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val id = Reg(UInt(log2Up(p.rfLockCount+1) bits))
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val commited = Reg(Bool)
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val write = Reg(Bool)
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val init = new Area{
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val counter = Reg(UInt(6 bits)) init(0)
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val done = CombInit(counter.msb)
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when(!done){
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counter := counter + 1
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}
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def apply(port : Flow[MemWriteCmd[Bool]]) = {
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port.valid := !done
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port.address := counter.resized
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port.data := False
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port
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}
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}
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val lockFree = !lock.map(_.valid).andR
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val lockFreeId = OHMasking.first(lock.map(!_.valid))
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val scoreboards = Array.fill(portCount)(new Area{
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val target, hit = Mem(Bool, 32) // XOR
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val writes = Mem(Bool, 32)
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val targetWrite = init(target.writePort)
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val hitWrite = init(hit.writePort)
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})
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}
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// val completion = for(source <- 0 until portCount) yield new Area{
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@ -202,85 +204,97 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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}
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val commitLogic = for(source <- 0 until portCount) yield new Area{
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val fire = False
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val target, hit = Reg(UInt(log2Up(p.rfLockCount+1) bits)) init(0)
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val full = target + 1 === hit
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when(fire){
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hit := hit + 1
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}
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class Tracker(width : Int) extends Area{
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val counter = Reg(UInt(width bits)) init(0)
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val full = counter.andR
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val notEmpty = counter.orR
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val inc = False
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val dec = False
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counter := counter + U(inc) - U(dec)
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}
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commitFork.commit(source).ready := False
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when(commitFork.commit(source).valid) {
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for (lock <- rf.lock) {
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when(lock.valid && lock.source === source && lock.id === hit && !lock.commited) {
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fire := True
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lock.commited := True
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lock.write := commitFork.commit(source).write
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commitFork.commit(source).ready := True
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}
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}
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class CommitArea(source : Int) extends Area{
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val add, mul, div, sqrt, short = new Tracker(4)
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val input = commitFork.commit(source).haltWhen(List(add, mul, div, sqrt, short).map(_.full).orR).toFlow
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when(input.fire){
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add.inc setWhen(List(FpuOpcode.ADD).map(input.opcode === _).orR)
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mul.inc setWhen(List(FpuOpcode.MUL, FpuOpcode.FMA).map(input.opcode === _).orR)
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div.inc setWhen(List(FpuOpcode.DIV).map(input.opcode === _).orR)
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sqrt.inc setWhen(List(FpuOpcode.SQRT).map(input.opcode === _).orR)
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short.inc setWhen(List(FpuOpcode.SGNJ, FpuOpcode.MIN_MAX, FpuOpcode.FCVT_X_X).map(input.opcode === _).orR)
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rf.scoreboards(source).writes(input.rd) := input.write
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}
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}
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val read = new Area{
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val arbiter = StreamArbiterFactory.noLock.roundRobin.build(FpuCmd(p), portCount)
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arbiter.io.inputs <> Vec(io.port.map(_.cmd))
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val commitLogic = for(source <- 0 until portCount) yield new CommitArea(source)
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val arbiterOutput = Stream(RfReadInput())
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arbiterOutput.arbitrationFrom(arbiter.io.output)
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arbiterOutput.source := arbiter.io.chosen
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arbiterOutput.payload.assignSomeByName(arbiter.io.output.payload)
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def commitConsume(what : CommitArea => Tracker, source : UInt, fire : Bool) : Bool = {
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for(i <- 0 until portCount) what(commitLogic(i)).dec setWhen(fire && source === i)
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commitLogic.map(what(_).notEmpty).read(source)
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}
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val s0 = arbiterOutput.pipelined(m2s = true, s2m = true) //TODO may need to remove m2s for store latency
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val scheduler = for(portId <- 0 until portCount;
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scoreboard = rf.scoreboards(portId)) yield new Area{
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val input = io.port(portId).cmd.combStage()
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val useRs1, useRs2, useRs3, useRd = False
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switch(s0.opcode){
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is(p.Opcode.LOAD) { useRd := True }
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is(p.Opcode.STORE) { useRs1 := True }
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is(p.Opcode.ADD) { useRd := True; useRs1 := True; useRs2 := True }
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is(p.Opcode.MUL) { useRd := True; useRs1 := True; useRs2 := True }
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is(p.Opcode.DIV) { useRd := True; useRs1 := True; useRs2 := True }
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is(p.Opcode.SQRT) { useRd := True; useRs1 := True }
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is(p.Opcode.FMA) { useRd := True; useRs1 := True; useRs2 := True; useRs3 := True }
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is(p.Opcode.I2F) { useRd := True }
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is(p.Opcode.F2I) { useRs1 := True }
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is(p.Opcode.MIN_MAX) { useRd := True; useRs1 := True; useRs2 := True }
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is(p.Opcode.CMP) { useRs1 := True; useRs2 := True }
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is(p.Opcode.SGNJ) { useRd := True; useRs1 := True; useRs2 := True }
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is(p.Opcode.FMV_X_W) { useRs1 := True }
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is(p.Opcode.FMV_W_X) { useRd := True }
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is(p.Opcode.FCLASS ) { useRs1 := True }
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switch(input.opcode){
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is(p.Opcode.LOAD) { useRd := True }
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is(p.Opcode.STORE) { useRs1 := True }
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is(p.Opcode.ADD) { useRd := True; useRs1 := True; useRs2 := True }
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is(p.Opcode.MUL) { useRd := True; useRs1 := True; useRs2 := True }
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is(p.Opcode.DIV) { useRd := True; useRs1 := True; useRs2 := True }
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is(p.Opcode.SQRT) { useRd := True; useRs1 := True }
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is(p.Opcode.FMA) { useRd := True; useRs1 := True; useRs2 := True; useRs3 := True }
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is(p.Opcode.I2F) { useRd := True }
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is(p.Opcode.F2I) { useRs1 := True }
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is(p.Opcode.MIN_MAX) { useRd := True; useRs1 := True; useRs2 := True }
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is(p.Opcode.CMP) { useRs1 := True; useRs2 := True }
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is(p.Opcode.SGNJ) { useRd := True; useRs1 := True; useRs2 := True }
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is(p.Opcode.FMV_X_W) { useRs1 := True }
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is(p.Opcode.FMV_W_X) { useRd := True }
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is(p.Opcode.FCLASS ) { useRs1 := True }
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is(p.Opcode.FCVT_X_X ) { useRd := True; useRs1 := True }
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}
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val hits = List((useRs1, s0.rs1), (useRs2, s0.rs2), (useRs3, s0.rs3), (useRd, s0.rd)).map{case (use, reg) => use && rf.lock.map(l => l.valid && l.source === s0.source && l.address === reg).orR}
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val hazard = hits.orR || commitLogic.map(_.full).read(s0.source)
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when(s0.fire && useRd){
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for(i <- 0 until portCount){
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when(s0.source === i){
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commitLogic(i).target := commitLogic(i).target + 1
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}
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}
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for(i <- 0 until p.rfLockCount){
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when(rf.lockFreeId(i)){
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rf.lock(i).valid := True
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rf.lock(i).source := s0.source
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rf.lock(i).address := s0.rd
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rf.lock(i).id := commitLogic.map(_.target).read(s0.source)
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rf.lock(i).commited := False
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}
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}
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}
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val uses = List(useRs1, useRs2, useRs3, useRd)
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val regs = List(input.rs1, input.rs2, input.rs3, input.rd)
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val rfHits = regs.map(scoreboard.hit.readAsync(_))
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val rfTargets = regs.map(scoreboard.target.readAsync(_))
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val rfBusy = (rfHits, rfTargets).zipped.map(_ ^ _)
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val s1 = s0.haltWhen(hazard || !rf.lockFree).m2sPipe()
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val hits = (0 to 3).map(id => uses(id) && rfBusy(id))
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val hazard = hits.orR || !rf.init.done
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val output = input.haltWhen(hazard)
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when(input.valid && rf.init.done){
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scoreboard.targetWrite.address := input.rd
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scoreboard.targetWrite.data := !rfTargets.last
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}
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when(output.fire && useRd){
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scoreboard.targetWrite.valid := True
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}
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}
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val cmdArbiter = new Area{
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val arbiter = StreamArbiterFactory.noLock.roundRobin.build(FpuCmd(p), portCount)
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arbiter.io.inputs <> Vec(scheduler.map(_.output))
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val output = arbiter.io.output.swapPayload(RfReadInput())
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output.source := arbiter.io.chosen
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output.payload.assignSomeByName(arbiter.io.output.payload)
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}
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val read = new Area{
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val s0 = cmdArbiter.output.pipelined(m2s = true, s2m = true) //TODO may need to remove m2s for store latency
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val s1 = s0.m2sPipe()
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val output = s1.swapPayload(RfReadOutput())
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val s1LockId = RegNextWhen(OHToUInt(rf.lockFreeId), !output.isStall)
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val rs1Entry = rf.ram.readSync(s0.source @@ s0.rs1,enable = !output.isStall)
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val rs2Entry = rf.ram.readSync(s0.source @@ s0.rs2,enable = !output.isStall)
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val rs3Entry = rf.ram.readSync(s0.source @@ s0.rs3,enable = !output.isStall)
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output.source := s1.source
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output.opcode := s1.opcode
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output.lockId := s1LockId
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output.arg := s1.arg
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output.roundMode := s1.roundMode
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output.rd := s1.rd
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@ -397,6 +411,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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add.payload.assignSomeByName(input.payload)
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add.rs2.sign.allowOverride;
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add.rs2.sign := input.rs2.sign ^ input.arg(0)
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add.needCommit := True
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}
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}
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}
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@ -405,7 +420,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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case class S0() extends Bundle{
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val source = Source()
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val lockId = lockIdType()
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val rd = p.rfAddress()
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val value = p.storeLoadType()
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val i2f = Bool()
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@ -416,15 +430,15 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val s0 = new Area{
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val input = decode.load.pipelined(m2s = true, s2m = true)
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val filtred = commitFork.load.map(port => port.takeWhen(port.sync))
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val filtred = commitFork.load.map(port => port.takeWhen(List(FpuOpcode.LOAD, FpuOpcode.FMV_W_X, FpuOpcode.I2F).map(_ === port.opcode).orR))
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def feed = filtred(input.source)
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val hazard = !feed.valid
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val output = input.haltWhen(hazard).swapPayload(S0())
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filtred.foreach(_.ready := False)
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feed.ready := input.valid && output.ready
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output.source := input.source
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output.lockId := input.lockId
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output.rd := input.rd
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output.value := feed.value
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output.i2f := input.i2f
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@ -555,10 +569,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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when(isInfinity){recoded.setInfinity}
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when(isNan){recoded.setNan}
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val isCommited = rf.lock.map(_.commited).read(input.lockId)
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val output = input.haltWhen(busy || !isCommited).swapPayload(new MergeInput())
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val output = input.haltWhen(busy).swapPayload(new MergeInput())
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output.source := input.source
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output.lockId := input.lockId
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output.roundMode := input.roundMode
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if(p.withDouble) {
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output.format := input.format
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@ -589,9 +601,10 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val shortPip = new Area{
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val input = decode.shortPip.stage()
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val toFpuRf = List(FpuOpcode.MIN_MAX, FpuOpcode.SGNJ, FpuOpcode.FCVT_X_X).map(input.opcode === _).orR
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val rfOutput = Stream(new MergeInput())
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val isCommited = rf.lock.map(_.commited).read(input.lockId)
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val isCommited = commitConsume(_.short, input.source, input.fire && toFpuRf)
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val output = rfOutput.haltWhen(!isCommited)
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val result = p.storeLoadType().assignDontCare()
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@ -809,11 +822,9 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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is(FpuOpcode.FCLASS) { result(31 downto 0) := fclassResult.resized }
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}
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val toFpuRf = List(FpuOpcode.MIN_MAX, FpuOpcode.SGNJ, FpuOpcode.FCVT_X_X).map(input.opcode === _).orR
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rfOutput.valid := input.valid && toFpuRf && !halt
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rfOutput.source := input.source
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rfOutput.lockId := input.lockId
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rfOutput.rd := input.rd
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rfOutput.roundMode := input.roundMode
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if(p.withDouble) rfOutput.format := input.format
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@ -930,8 +941,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val input = mul.output.stage()
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val sum = splits.take(sumSplitAt).map(e => (input.muls(e.id) << e.offsetC).resize(outWidth)).reduceBalancedTree(_ + _)
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val isCommited = rf.lock.map(_.commited).read(input.lockId)
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val output = input.haltWhen(!isCommited).swapPayload(new Sum1Output())
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val output = input.swapPayload(new Sum1Output())
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output.payload.assignSomeByName(input.payload)
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output.mulC2 := sum.resized
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output.muls2 := Vec(input.muls.drop(sumSplitAt))
|
||||
|
|
@ -941,7 +951,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
|
|||
val input = sum1.output.stage()
|
||||
val sum = input.mulC2 + splits.drop(sumSplitAt).map(e => (input.muls2(e.id-sumSplitAt) << e.offsetC).resize(outWidth)).reduceBalancedTree(_ + _)
|
||||
|
||||
val isCommited = rf.lock.map(_.commited).read(input.lockId)
|
||||
val isCommited = commitConsume(_.mul, input.source, input.fire)
|
||||
val output = input.haltWhen(!isCommited).swapPayload(new Sum2Output())
|
||||
output.payload.assignSomeByName(input.payload)
|
||||
output.mulC := sum
|
||||
|
|
@ -998,7 +1008,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
|
|||
val output = Stream(new MergeInput())
|
||||
output.valid := input.valid && !input.add && !input.divSqrt
|
||||
output.source := input.source
|
||||
output.lockId := input.lockId
|
||||
output.rd := input.rd
|
||||
if (p.withDouble) output.format := input.format
|
||||
output.roundMode := input.roundMode
|
||||
|
|
@ -1015,8 +1024,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
|
|||
decode.mulToAdd.rs1.special := norm.output.special
|
||||
decode.mulToAdd.rs2 := input.rs3
|
||||
decode.mulToAdd.rd := input.rd
|
||||
decode.mulToAdd.lockId := input.lockId
|
||||
decode.mulToAdd.roundMode := input.roundMode
|
||||
decode.mulToAdd.needCommit := False
|
||||
if (p.withDouble) decode.mulToAdd.format := input.format
|
||||
|
||||
when(NV){
|
||||
|
|
@ -1031,7 +1040,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
|
|||
val div = p.withDiv generate new Area{
|
||||
val input = decode.div.halfPipe()
|
||||
val haltIt = True
|
||||
val isCommited = RegNext(rf.lock.map(_.commited).read(input.lockId))
|
||||
val isCommited = RegNext(commitConsume(_.div, input.source, input.fire))
|
||||
val output = input.haltWhen(haltIt || !isCommited).swapPayload(new MergeInput())
|
||||
|
||||
val dividerShift = if(p.withDouble) 0 else 1
|
||||
|
|
@ -1096,7 +1105,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
|
|||
val sqrt = p.withSqrt generate new Area{
|
||||
val input = decode.sqrt.halfPipe()
|
||||
val haltIt = True
|
||||
val isCommited = RegNext(rf.lock.map(_.commited).read(input.lockId))
|
||||
val isCommited = RegNext(commitConsume(_.sqrt, input.source, input.fire))
|
||||
val output = input.haltWhen(haltIt || !isCommited).swapPayload(new MergeInput())
|
||||
|
||||
val needShift = !input.rs1.exponent.lsb
|
||||
|
|
@ -1170,7 +1179,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
|
|||
|
||||
val divSqrt = p.withDivSqrt generate new Area {
|
||||
val input = decode.divSqrt.halfPipe()
|
||||
|
||||
assert(false, "Need to implement commit tracking")
|
||||
val aproxWidth = 8
|
||||
val aproxDepth = 64
|
||||
val divIterationCount = 3
|
||||
|
|
@ -1188,7 +1197,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
|
|||
decode.divSqrtToMul.rs2.assignDontCare()
|
||||
decode.divSqrtToMul.rs3.assignDontCare()
|
||||
decode.divSqrtToMul.rd := input.rd
|
||||
decode.divSqrtToMul.lockId := input.lockId
|
||||
decode.divSqrtToMul.add := False
|
||||
decode.divSqrtToMul.divSqrt := True
|
||||
decode.divSqrtToMul.msb1 := True
|
||||
|
|
@ -1420,8 +1428,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
|
|||
|
||||
val oh = new Area {
|
||||
val input = math.output.stage()
|
||||
val isCommited = rf.lock.map(_.commited).read(input.lockId)
|
||||
val output = input.haltWhen(!isCommited).swapPayload(new OhOutput)
|
||||
val isCommited = commitConsume(_.add, input.source, input.fire && input.needCommit)
|
||||
val output = input.haltWhen(input.needCommit && !isCommited).swapPayload(new OhOutput)
|
||||
output.payload.assignSomeByName(input.payload)
|
||||
import input.payload._
|
||||
|
||||
|
|
@ -1462,7 +1470,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
|
|||
import input.payload._
|
||||
|
||||
output.source := input.source
|
||||
output.lockId := input.lockId
|
||||
output.rd := input.rd
|
||||
output.value.sign := xySign
|
||||
output.value.mantissa := (mantissa >> 2).resized
|
||||
|
|
@ -1620,14 +1627,14 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
|
|||
|
||||
|
||||
nx setWhen(!input.value.special && (roundAdjusted =/= 0))
|
||||
val write = rf.lock.map(_.write).read(input.lockId)
|
||||
val writes = rf.scoreboards.map(_.writes.readAsync(input.rd))
|
||||
val write = writes.toList.read(input.source)
|
||||
output.NX := nx & write
|
||||
output.OF := of & write
|
||||
output.UF := uf & write
|
||||
output.NV := input.NV & write
|
||||
output.DZ := input.DZ & write
|
||||
output.source := input.source
|
||||
output.lockId := input.lockId
|
||||
output.rd := input.rd
|
||||
output.write := write
|
||||
if(p.withDouble) output.format := input.format
|
||||
|
|
@ -1649,8 +1656,11 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
|
|||
}
|
||||
|
||||
when(input.valid){
|
||||
for(i <- 0 until p.rfLockCount) when(input.lockId === i){
|
||||
rf.lock(i).valid := False
|
||||
for(i <- 0 until portCount) {
|
||||
val port = rf.scoreboards(i).hitWrite
|
||||
port.valid setWhen(input.source === i)
|
||||
port.address := input.rd
|
||||
port.data := !rf.scoreboards(i).hit(input.rd) //TODO improve
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1852,6 +1862,19 @@ object FpuSynthesisBench extends App{
|
|||
//Artix 7 -> 106 Mhz 3322 LUT 3023 FF
|
||||
//Artix 7 -> 161 Mhz 3675 LUT 3163 FF
|
||||
|
||||
//Fpu_32 ->
|
||||
//Artix 7 -> 132 Mhz 1891 LUT 1837 FF
|
||||
//Artix 7 -> 209 Mhz 2132 LUT 1847 FF
|
||||
//Fpu_64 ->
|
||||
//Artix 7 -> 105 Mhz 3348 LUT 3024 FF
|
||||
//Artix 7 -> 162 Mhz 3712 LUT 3165 FF
|
||||
|
||||
//Fpu_32 ->
|
||||
//Artix 7 -> 128 Mhz 1796 LUT 1727 FF
|
||||
//Artix 7 -> 208 Mhz 2049 LUT 1727 FF
|
||||
//Fpu_64 ->
|
||||
//Artix 7 -> 109 Mhz 3417 LUT 2913 FF
|
||||
//Artix 7 -> 168 Mhz 3844 LUT 3053 FF
|
||||
|
||||
/*
|
||||
testfloat -tininessafter -all1 > all1.txt
|
||||
|
|
|
|||
|
|
@ -118,7 +118,6 @@ object FpuRoundModeInstr extends SpinalEnum(){
|
|||
case class FpuParameter( withDouble : Boolean,
|
||||
mulWidthA : Int = 18,
|
||||
mulWidthB : Int = 18,
|
||||
rfLockCount : Int = 8,
|
||||
sim : Boolean = false,
|
||||
withAdd : Boolean = true,
|
||||
withMul : Boolean = true,
|
||||
|
|
@ -160,8 +159,9 @@ case class FpuCmd(p : FpuParameter) extends Bundle{
|
|||
}
|
||||
|
||||
case class FpuCommit(p : FpuParameter) extends Bundle{
|
||||
val opcode = FpuOpcode()
|
||||
val rd = UInt(5 bits)
|
||||
val write = Bool()
|
||||
val sync = Bool()
|
||||
val value = p.storeLoadType() // IEEE 754
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ class FpuPlugin(externalFpu : Boolean = false,
|
|||
object FPU_ARG extends Stageable(Bits(2 bits))
|
||||
object FPU_FORMAT extends Stageable(FpuFormat())
|
||||
|
||||
var port : FpuPort = null
|
||||
var port : FpuPort = null //Commit port is already isolated
|
||||
|
||||
override def getVexRiscvRegressionArgs(): Seq[String] = {
|
||||
var args = List[String]()
|
||||
|
|
@ -331,7 +331,8 @@ class FpuPlugin(externalFpu : Boolean = false,
|
|||
commit.value(31 downto 0) := (input(FPU_COMMIT_LOAD) ? dBusEncoding.loadData()(31 downto 0) | input(RS1))
|
||||
if(p.withDouble) commit.value(63 downto 32) := dBusEncoding.loadData()(63 downto 32)
|
||||
commit.write := arbitration.isValid && !arbitration.removeIt
|
||||
commit.sync := input(FPU_COMMIT_SYNC)
|
||||
commit.opcode := input(FPU_OPCODE)
|
||||
commit.rd := input(INSTRUCTION)(rdRange).asUInt
|
||||
|
||||
when(isCommit && !commit.ready){
|
||||
arbitration.haltByOther := True
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
|
||||
def testP(p : FpuParameter){
|
||||
val portCount = 1
|
||||
val portCount = 4
|
||||
|
||||
val config = SimConfig
|
||||
config.allOptimisation
|
||||
|
|
@ -276,8 +276,9 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.rd #= rd
|
||||
cmd.value #= value
|
||||
cmd.sync #= true
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.LOAD
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -326,7 +327,8 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.sync #= false
|
||||
cmd.rd #= rd
|
||||
cmd.opcode #= opcode
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -404,7 +406,8 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.sync #= true
|
||||
cmd.rd #= rd
|
||||
cmd.opcode #= FpuOpcode.I2F
|
||||
cmd.value #= value.toLong & 0xFFFFFFFFl
|
||||
}
|
||||
}
|
||||
|
|
@ -436,7 +439,8 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.sync #= true
|
||||
cmd.rd #= rd
|
||||
cmd.opcode #= FpuOpcode.FMV_W_X
|
||||
cmd.value #= value.toLong & 0xFFFFFFFFl
|
||||
}
|
||||
}
|
||||
|
|
@ -454,7 +458,8 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.sync #= false
|
||||
cmd.rd #= rd
|
||||
cmd.opcode #= FpuOpcode.MIN_MAX
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue