Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add ASID field to SATP 

ASID field is missing from the SATP which causes compatibility
issues with Xous.

While this patch resolves the Xous issue, it has not been tested
on Linux.
This commit is contained in:
bunnie 2020-10-04 15:34:58 +08:00
parent 5f0c7a7faf
commit 65e6f6054b
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/vexriscv/plugin/MmuPlugin.scala
View File

@ -91,11 +91,12 @@ class MmuPlugin(ioRange : UInt => Bool,
} }
val satp = new Area { val satp = new Area {
val mode = RegInit(False) val mode = RegInit(False)
val asid = Reg(Bits(9 bits))
val ppn = Reg(UInt(20 bits)) val ppn = Reg(UInt(20 bits))
} }
for(offset <- List(CSR.MSTATUS, CSR.SSTATUS)) csrService.rw(offset, 19 -> status.mxr, 18 -> status.sum, 17 -> status.mprv) for(offset <- List(CSR.MSTATUS, CSR.SSTATUS)) csrService.rw(offset, 19 -> status.mxr, 18 -> status.sum, 17 -> status.mprv)
csrService.rw(CSR.SATP, 31 -> satp.mode, 0 -> satp.ppn) csrService.rw(CSR.SATP, 31 -> satp.mode, 22 -> satp.asid, 0 -> satp.ppn)
} }
val core = pipeline plug new Area { val core = pipeline plug new Area {