Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Privileged debug now implement stoptime stopcount

This commit is contained in:
Dolu1990 2022-11-17 13:58:25 +01:00
parent 36c3346e51
commit 663174bc73
1 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -469,6 +469,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
var inWfi : Bool = null var inWfi : Bool = null
var externalMhartId : UInt = null var externalMhartId : UInt = null
var utime : UInt = null var utime : UInt = null
var stoptime : Bool = null
var debugBus : DebugHartBus = null var debugBus : DebugHartBus = null
var debugMode : Bool = null var debugMode : Bool = null
@ -752,8 +753,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
val nmip = False val nmip = False
val mprven = False val mprven = False
val cause = RegInit(U"000") val cause = RegInit(U"000")
val stoptime = False val stoptime = RegInit(False)
val stopcount = False val stopcount = RegInit(False)
val stepie = RegInit(False) //TODO val stepie = RegInit(False) //TODO
val ebreaku = userGen generate RegInit(False) val ebreaku = userGen generate RegInit(False)
val ebreaks = supervisorGen generate RegInit(False) val ebreaks = supervisorGen generate RegInit(False)
@ -801,8 +802,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
} }
r(CSR.DCSR, 3 -> nmip, 6 -> cause, 28 -> xdebugver, 4 -> mprven, 9 -> stoptime, 10 -> stopcount) r(CSR.DCSR, 3 -> nmip, 6 -> cause, 28 -> xdebugver, 4 -> mprven)
rw(CSR.DCSR, 0 -> prv, 2 -> step, 11 -> stepie, 15 -> ebreakm) rw(CSR.DCSR, 0 -> prv, 2 -> step, 9 -> stoptime, 10 -> stopcount, 11 -> stepie, 15 -> ebreakm)
if(supervisorGen) rw(CSR.DCSR, 13 -> ebreaks) if(supervisorGen) rw(CSR.DCSR, 13 -> ebreaks)
if(userGen) rw(CSR.DCSR, 12 -> ebreaku) if(userGen) rw(CSR.DCSR, 12 -> ebreaku)
@ -819,6 +820,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
wakeService.askWake() wakeService.askWake()
} }
} }
stoptime = out(debugMode && dcsr.stoptime).setName("stoptime")
//Very limited subset of the trigger spec //Very limited subset of the trigger spec
val trigger = (debugTriggers > 0) generate new Area { val trigger = (debugTriggers > 0) generate new Area {
@ -1088,7 +1090,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
val stagesFromExecute = pipeline.stages.dropWhile(_ != execute) val stagesFromExecute = pipeline.stages.dropWhile(_ != execute)
//Manage counters //Manage counters
mcycle := mcycle + 1 mcycle := mcycle + (if(withPrivilegedDebug) U(!debugMode || !debug.dcsr.stopcount) else U(1))
when(lastStage.arbitration.isFiring) { when(lastStage.arbitration.isFiring) {
minstret := minstret + 1 minstret := minstret + 1
} }