Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Update Bmb invalidate/sync parameters

This commit is contained in:
Dolu1990 2021-07-28 13:44:04 +02:00
parent ba8f5f966a
commit 671bd30953
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/vexriscv/ip/DataCache.scala
View File

@ -100,11 +100,11 @@ case class DataCacheConfig(cacheSize : Int,
contextWidth = (if(!withWriteResponse) 1 else 0) + aggregationWidth, contextWidth = (if(!withWriteResponse) 1 else 0) + aggregationWidth,
alignment = BmbParameter.BurstAlignement.LENGTH, alignment = BmbParameter.BurstAlignement.LENGTH,
canExclusive = withExclusive, canExclusive = withExclusive,
withCachedRead = true withCachedRead = true,
canInvalidate = withInvalidate,
canSync = withInvalidate
)), )),
BmbInvalidationParameter( BmbInvalidationParameter(
canInvalidate = withInvalidate,
canSync = withInvalidate,
invalidateLength = log2Up(this.bytePerLine), invalidateLength = log2Up(this.bytePerLine),
invalidateAlignment = BmbParameter.BurstAlignement.LENGTH invalidateAlignment = BmbParameter.BurstAlignement.LENGTH
) )