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VexRiscv
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typo

This commit is contained in:
Charles Papon 2020-02-23 23:17:02 +01:00
parent c8016e90a4
commit 67d2071a32
2 changed files with 3 additions and 3 deletions
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2
src/main/scala/vexriscv/demo/SynthesisBench.scala
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@ -121,7 +121,7 @@ object VexRiscvSynthesisBench {
) ++ IcestormStdTargets().take(1)
// val targets = IcestormStdTargets()
Bench(rtls, targets, "/media/miaou/HD/linux/tmp")
Bench(rtls, targets, "/media/miaou/HD/linux/tmp/")
}
}

4
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -686,7 +686,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
//Aggregate all exception port and remove required instructions
val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{
val exceptionPortCtrl = exceptionPortsInfos.nonEmpty generate new Area{
val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min
val exceptionValids = Vec(stages.map(s => Bool().setPartialName(s.getName())))
val exceptionValidsRegs = Vec(stages.map(s => Reg(Bool).init(False).setPartialName(s.getName()))).allowUnsetRegToAvoidLatch
@ -763,7 +763,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
//Avoid the PC register of the last stage to change durring an exception handleing (Used to fill Xepc)
stages.last.dontSample.getOrElseUpdate(PC, ArrayBuffer[Bool]()) += exceptionValids.last
exceptionPendings := exceptionValidsRegs
} else null
}