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Tom Verbeure
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README.md
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README.md
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@ -57,7 +57,7 @@ For commercial support, please contact spinalhdl@gmail.com.
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## Area usage and maximal frequency
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The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral).<br>
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The clock constraint is set to a unattainable value, which tends to increase the design area.<br>
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The clock constraint is set to an unattainable value, which tends to increase the design area.<br>
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The dhrystone benchmark was compiled with the `-O3 -fno-inline` option.<br>
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All the cached configurations have some cache trashing during the dhrystone benchmark except the `VexRiscv full max perf` one. This of course reduces the performance. It is possible to produce
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dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case.<br>
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@ -253,7 +253,7 @@ To generate the Briey SoC Hardware:
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sbt "run-main vexriscv.demo.Briey"
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```
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To run the verilator simulation of the Briey SoC which can be then connected to OpenOCD/GDB, first get those dependencies:
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To run the verilator simulation of the Briey SoC which can then be connected to OpenOCD/GDB, first get those dependencies:
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```sh
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sudo apt-get install build-essential xorg-dev libudev-dev libts-dev libgl1-mesa-dev libglu1-mesa-dev libasound2-dev libpulse-dev libopenal-dev libogg-dev libvorbis-dev libaudiofile-dev libpng12-dev libfreetype6-dev libusb-dev libdbus-1-dev zlib1g-dev libdirectfb-dev libsdl2-dev
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@ -271,9 +271,9 @@ To connect OpenOCD (https://github.com/SpinalHDL/openocd_riscv) to the simulatio
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src/openocd -f tcl/interface/jtag_tcp.cfg -c "set BRIEY_CPU0_YAML /home/spinalvm/Spinal/VexRiscv/cpu0.yaml" -f tcl/target/briey.cfg
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```
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You can find multiples software examples and demos here: https://github.com/SpinalHDL/VexRiscvSocSoftware/tree/master/projects/briey
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You can find multiple software examples and demos here: https://github.com/SpinalHDL/VexRiscvSocSoftware/tree/master/projects/briey
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You can find some FPGA project which instantiate the Briey SoC there (DE1-SoC, DE0-Nano): https://drive.google.com/drive/folders/0B-CqLXDTaMbKZGdJZlZ5THAxRTQ?usp=sharing
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You can find some FPGA projects which instantiate the Briey SoC here (DE1-SoC, DE0-Nano): https://drive.google.com/drive/folders/0B-CqLXDTaMbKZGdJZlZ5THAxRTQ?usp=sharing
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Here are some measurements of Briey SoC timings and area :
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@ -369,7 +369,7 @@ sudo mv /opt/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6 /opt/riscv
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echo 'export PATH=/opt/riscv/bin:$PATH' >> ~/.bashrc
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```
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If you want to compile from rv32i and rv32im gcc from source code and install them in /opt/, do the following (will take one hour):
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If you want to compile the rv32i and rv32im GCC toolchain from source code and install them in `/opt/`, do the following (will take one hour):
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```sh
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# Be carefull, sometime the git clone has issue to successfully clone riscv-gnu-toolchain.
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@ -400,7 +400,9 @@ echo -e "\\nRISC-V Toolchain installation completed!"
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## CPU parametrization and instantiation example
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You can find many examples of different configurations in the https://github.com/SpinalHDL/VexRiscv/tree/master/src/main/scala/vexriscv/demo folder. Here is one such example:
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You can find many examples of different configurations in the https://github.com/SpinalHDL/VexRiscv/tree/master/src/main/scala/vexriscv/demo folder.
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Here is one such example:
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```scala
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import vexriscv._
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@ -535,7 +537,7 @@ class SimdAddPlugin extends Plugin[VexRiscv]{
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}
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```
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If you want to add this plugin to a given CPU, you just need to add it in its parameterized plugin list.
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If you want to add this plugin to a given CPU, you just need to add it to its parameterized plugin list.
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This example is a very simple one, but each plugin can really have access to the whole CPU:
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- Halt a given stage of the CPU
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@ -576,7 +578,7 @@ The second one (`CustomCsrDemoGpioPlugin`) creates a GPIO peripheral directly ma
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## CPU clock and resets
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Without the debug plugin, the CPU will have `clk` input and a `reset` input, which is very standard. But with the debug plugin the situation is the following :
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Without the debug plugin, the CPU will have a standard `clk` input and a `reset` input. But with the debug plugin the situation is the following :
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- clk : As before, the clock which drive the whole CPU design, including the debug logic
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- reset : Reset all the CPU states excepted the debug logics
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@ -604,14 +606,15 @@ toplevelReset >----+--------> debugReset |
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## VexRiscv Architecture
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VexRiscv is implemented via a 5 stage in-order pipeline on which many optional and complementary plugins add functionalities to provide a functional RISC-V CPU.
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This approach is completely unconventional and only possible on meta hardware description languages (SpinalHDL in the current case) but has proven its advantages via the VexRiscv implementation:
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This approach is completely unconventional and only possible through meta hardware description languages (SpinalHDL in the current case) but has proven its advantages
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via the VexRiscv implementation:
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- You can swap/turn on/turn off parts of the CPU directly via the plugin system
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- You can add new functionalities/instruction without having to modify any sources code of the CPU
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- It allows the CPU configuration to cover a very large spectrum of implementation without cooking spaghetti code
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- It allows your code base to truly produce a parametrized CPU design
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If you generate the CPU without any plugin, it will only contain the definition of the 5 stages and their basic arbitration, but nothing else,
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If you generate the CPU without any plugin, it will only contain the definition of the 5 pipeline stages and their basic arbitration, but nothing else,
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as everything else, including the program counter is added into the CPU via plugins.
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### Plugins
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@ -722,7 +725,7 @@ Simple and light multi-way instruction cache.
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| catchAccessFault | Boolean | Catch when the memeory bus is responding with an error |
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| catchMemoryTranslationMiss | Boolean | Catch when the MMU miss a TLB |
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Note: If you enable the twoCycleRam and the wayCount is bigger than one, then the register file plugin should be configured to read the regFile in a asynchronous manner.
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Note: If you enable the twoCycleRam option and if wayCount is bigger than one, then the register file plugin should be configured to read the regFile in a asynchronous manner.
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#### DecoderSimplePlugin
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