Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add CsrPlugin ebreak support

This commit is contained in:
Dolu1990 2018-10-10 19:23:04 +02:00
parent 0662cc2797
commit 68f1ff3222
1 changed files with 11 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -51,6 +51,7 @@ case class CsrPluginConfig(
ucycleAccess : CsrAccess, ucycleAccess : CsrAccess,
wfiGen : Boolean, wfiGen : Boolean,
ecallGen : Boolean, ecallGen : Boolean,
ebreakGen : Boolean = false,
supervisorGen : Boolean = false, supervisorGen : Boolean = false,
sscratchGen : Boolean = false, sscratchGen : Boolean = false,
stvecAccess : CsrAccess = CsrAccess.NONE, stvecAccess : CsrAccess = CsrAccess.NONE,
@ -66,7 +67,7 @@ case class CsrPluginConfig(
){ ){
assert(!ucycleAccess.canWrite) assert(!ucycleAccess.canWrite)
def noException = this.copy(ecallGen = false, catchIllegalAccess = false) def noException = this.copy(ecallGen = false, ebreakGen = false, catchIllegalAccess = false)
} }
object CsrPluginConfig{ object CsrPluginConfig{
@ -248,6 +249,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
val NONE, XRET = newElement() val NONE, XRET = newElement()
val WFI = if(wfiGen) newElement() else null val WFI = if(wfiGen) newElement() else null
val ECALL = if(ecallGen) newElement() else null val ECALL = if(ecallGen) newElement() else null
val EBREAK = if(ebreakGen) newElement() else null
} }
object ENV_CTRL extends Stageable(EnvCtrlEnum()) object ENV_CTRL extends Stageable(EnvCtrlEnum())
@ -304,6 +306,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
)) ))
if(wfiGen) decoderService.add(WFI, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.WFI)) if(wfiGen) decoderService.add(WFI, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.WFI))
if(ecallGen) decoderService.add(ECALL, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.ECALL, HAS_SIDE_EFFECT -> True)) if(ecallGen) decoderService.add(ECALL, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.ECALL, HAS_SIDE_EFFECT -> True))
if(ebreakGen) decoderService.add(EBREAK, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.EBREAK, HAS_SIDE_EFFECT -> True))
val pcManagerService = pipeline.service(classOf[JumpService]) val pcManagerService = pipeline.service(classOf[JumpService])
jumpInterface = pcManagerService.createJumpInterface(pipeline.writeBack) jumpInterface = pcManagerService.createJumpInterface(pipeline.writeBack)
@ -321,7 +324,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
privilege = RegInit(U"11").setName("CsrPlugin_privilege") privilege = RegInit(U"11").setName("CsrPlugin_privilege")
if(catchIllegalAccess || ecallGen) if(catchIllegalAccess || ecallGen || ebreakGen)
selfException = newExceptionPort(pipeline.execute) selfException = newExceptionPort(pipeline.execute)
allowInterrupts = True allowInterrupts = True
@ -762,6 +765,12 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
} }
if(ebreakGen) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.EBREAK){
selfException.valid := True
selfException.code := 3
}
val imm = IMM(input(INSTRUCTION)) val imm = IMM(input(INSTRUCTION))
val writeSrc = input(REGFILE_WRITE_DATA) val writeSrc = input(REGFILE_WRITE_DATA)
val readData = B(0, 32 bits) val readData = B(0, 32 bits)