Remove mepc from smallest CSR config

Better readme

README.md

@@ -58,10 +58,10 @@ NOTE :
 The VexRiscv could need the unreleased master-head of SpinalHDL. If it fail to compile, just get the SpinalHDL repository and do a "sbt publish-local" in it.
 
 ```sh
-sbt "run-main VexRiscv.GenFull"
+sbt "run-main VexRiscv.demo.GenFull"
 
 # or
-sbt "run-main VexRiscv.GenSmallest"
+sbt "run-main VexRiscv.demo.GenSmallest"
 ```
 
 ## Tests
@@ -83,7 +83,7 @@ Then you can use the https://github.com/SpinalHDL/openocd_riscv tool to create a
 
 ```sh
 #in the VexRiscv repository, to run the simulation on which one OpenOCD can connect itself =>
-sbt "run-main VexRiscv.GenFull"
+sbt "run-main VexRiscv.demo.GenFull"
 cd src/test/cpp/regression
 make run DEBUG_PLUGIN_EXTERNAL=yes
 
@@ -125,7 +125,7 @@ sudo apt-get install build-essential xorg-dev libudev-dev libts-dev libgl1-mesa-
 Then go in src/test/cpp/briey and run the simulation with (UART TX is printed in the terminal, VGA is displayed in a GUI):
 
 ```sh
-make clean
+make clean run
 ```
 
 To connect OpenOCD (https://github.com/SpinalHDL/openocd_riscv) to the simulation :

src/main/scala/VexRiscv/Plugin/CsrPlugin.scala

@@ -107,7 +107,7 @@ object CsrPluginConfig{
     misaAccess     = CsrAccess.NONE,
     mtvecAccess    = CsrAccess.NONE,
     mtvecInit      = 0x00000020l,
-    mepcAccess     = CsrAccess.READ_ONLY,
+    mepcAccess     = CsrAccess.NONE,
     mscratchGen    = false,
     mcauseAccess   = CsrAccess.READ_ONLY,
     mbadaddrAccess = CsrAccess.NONE,

src/main/scala/VexRiscv/demo/GenFull.scala

@@ -1,7 +1,8 @@
-package VexRiscv
+package VexRiscv.demo
 
 import VexRiscv.Plugin._
 import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig}
+import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig}
 import spinal.core._
 
 /**

src/main/scala/VexRiscv/demo/GenSmallest.scala

@@ -1,7 +1,7 @@
-package VexRiscv
+package VexRiscv.demo
 
 import VexRiscv.Plugin._
-import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig}
+import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig}
 import spinal.core._
 
 /**