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Merge pull request #397 from cherrypiejam/fix-smp-supervisor 

Fix SMP compile-time error when disabling supervisor option
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Dolu1990 2024-03-10 08:52:52 +01:00 committed by GitHub
parent e52251d88c 26d6f61d49
commit 6aeb6d4d43
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2 changed files with 8 additions and 1 deletions
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5
src/main/scala/vexriscv/VexRiscv.scala
View File

@ -53,6 +53,11 @@ case class VexRiscvConfig(){
case None => false
}
def withSupervisor = find(classOf[CsrPlugin]) match {
case Some(x) => x.config.supervisorGen
case None => false
}
def FLEN = if(withRvd) 64 else if(withRvf) 32 else 0
//Default Stageables

4
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
View File

@ -206,7 +206,9 @@ class VexRiscvSmpClusterWithPeripherals(p : VexRiscvSmpClusterParameter) extends
plic.priorityWidth.load(2)
plic.mapping.load(PlicMapping.sifive)
plic.addTarget(core.cpu.externalInterrupt)
plic.addTarget(core.cpu.externalSupervisorInterrupt)
if(core.cpu.config.withSupervisor) {
plic.addTarget(core.cpu.externalSupervisorInterrupt)
}
List(clint.logic, core.cpu.logic).produce {
for (plugin <- core.cpu.config.plugins) plugin match {
case plugin: CsrPlugin if plugin.utime != null => plugin.utime := clint.logic.io.time