Add LitexSoC workspace / linux loading. Need to emulate peripherals and adapte the kernel now. Probably also need some machine mode emulation Software time !
This commit is contained in:
Dolu1990
parent
0656a49332
commit
6c0608f0dd
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@ -26,8 +26,25 @@ import vexriscv._
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import vexriscv.ip._
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import vexriscv.plugin._
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/*
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Setup things =>
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git clone https://github.com/SpinalHDL/SpinalHDL.git -b dev
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git clone https://github.com/SpinalHDL/VexRiscv.git -b linux
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cd VexRiscv
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Run regressions =>
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sbt "runMain vexriscv.demo.LinuxGen -r"
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cd src/test/cpp/regression
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make run DBUS=SIMPLE IBUS=SIMPLE DHRYSTONE=yes SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=10 TRACE=no
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Run linux =>
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sbt "runMain vexriscv.demo.LinuxGen"
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cd src/test/cpp/regression
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make run DBUS=SIMPLE IBUS=SIMPLE SUPERVISOR=yes CSR=yes COMPRESSED=yes LITEX=yes VMLINUX=/home/spinalvm/hdl/linuxDave/vmlinux.bin RAMDISK=/home/spinalvm/hdl/linuxDave/initramdisk_dave TRACE=no
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*/
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object LinuxGen {
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def configFull(withMmu : Boolean = true) = {
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def configFull(litex : Boolean, withMmu : Boolean) = {
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val config = VexRiscvConfig(
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plugins = List(
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new IBusSimplePlugin(
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@ -171,15 +188,15 @@ object LinuxGen {
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)
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if(withMmu) config.plugins += new MmuPlugin(
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virtualRange = a => True,
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ioRange = _(31 downto 28) === 0xF,
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ioRange = (x => if(litex) x(31 downto 28) === 0xB || x(31 downto 28) === 0xE else x(31 downto 28) === 0xF),
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allowUserIo = true
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)
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config
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}
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def main(args: Array[String]) {
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// import spinal.core.sim._
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// SimConfig.withConfig(SpinalConfig(mergeAsyncProcess = false, anonymSignalPrefix = "zz_")).allOptimisation.compile(new VexRiscv(configFull)).doSimUntilVoid{ dut =>
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// dut.clockDomain.forkStimulus(10)
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@ -199,7 +216,10 @@ object LinuxGen {
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SpinalConfig(mergeAsyncProcess = true).generateVerilog {
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val toplevel = new VexRiscv(configFull())
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val toplevel = new VexRiscv(configFull(
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litex = !args.contains("-r"),
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withMmu = true
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))
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// val toplevel = new VexRiscv(configLight)
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// val toplevel = new VexRiscv(configTest)
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@ -288,13 +308,13 @@ object LinuxSyntesisBench extends App{
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val withoutMmu = new Rtl {
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override def getName(): String = "VexRiscv Without Mmu"
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override def getRtlPath(): String = "VexRiscvWithoutMmu.v"
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SpinalVerilog(new VexRiscv(LinuxGen.configFull(withMmu=false)).setDefinitionName(getRtlPath().split("\\.").head))
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SpinalVerilog(new VexRiscv(LinuxGen.configFull(litex = false, withMmu = false)).setDefinitionName(getRtlPath().split("\\.").head))
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}
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val withMmu = new Rtl {
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override def getName(): String = "VexRiscv With Mmu"
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override def getRtlPath(): String = "VexRiscvWithMmu.v"
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SpinalVerilog(new VexRiscv(LinuxGen.configFull(withMmu=true)).setDefinitionName(getRtlPath().split("\\.").head))
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SpinalVerilog(new VexRiscv(LinuxGen.configFull(litex = false, withMmu = true)).setDefinitionName(getRtlPath().split("\\.").head))
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}
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val rtls = List(withoutMmu, withMmu)
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@ -316,7 +336,7 @@ object LinuxSyntesisBench extends App{
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object LinuxSim extends App{
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import spinal.core.sim._
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SimConfig.allOptimisation.compile(new VexRiscv(LinuxGen.configFull())).doSim{dut =>
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SimConfig.allOptimisation.compile(new VexRiscv(LinuxGen.configFull(litex = false, withMmu = true))).doSim{dut =>
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// dut.clockDomain.forkStimulus(10)
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// dut.clockDomain.forkSimSpeedPrinter()
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// dut.plugins.foreach{
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@ -151,6 +151,26 @@ void loadHexImpl(string path,Memory* mem) {
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delete [] content;
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}
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void loadBinImpl(string path,Memory* mem, uint32_t offset) {
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FILE *fp = fopen(&path[0], "r");
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if(fp == 0){
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cout << path << " not found" << endl;
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}
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fseek(fp, 0, SEEK_END);
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uint32_t size = ftell(fp);
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fseek(fp, 0, SEEK_SET);
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char* content = new char[size];
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fread(content, 1, size, fp);
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fclose(fp);
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for(int byteId = 0; byteId < size;byteId++){
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*(mem->get(offset + byteId)) = content[byteId];
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}
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delete [] content;
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}
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#define TEXTIFY(A) #A
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@ -965,8 +985,8 @@ public:
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uint32_t seed;
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bool withInstructionReadCheck = true;
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void setIStall(bool enable) { iStall = enable; }
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void setDStall(bool enable) { dStall = enable; }
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Workspace* setIStall(bool enable) { iStall = enable; return this; }
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Workspace* setDStall(bool enable) { dStall = enable; return this; }
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ofstream regTraces;
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ofstream memTraces;
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@ -1027,7 +1047,7 @@ public:
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}
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if(address & (size-1) != 0)
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cout << "Ref did a unaligned read" << endl;
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if((address & 0xF0000000) == 0xF0000000){
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if(ws->isPerifRegion(address)){
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MemRead t = periphRead.front();
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if(t.address != address || t.size != size){
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fail();
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@ -1043,7 +1063,7 @@ public:
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virtual void dWrite(int32_t address, int32_t size, uint32_t data){
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if(address & (size-1) != 0)
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cout << "Ref did a unaligned write" << endl;
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if((address & 0xF0000000) == 0xF0000000){
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if(ws->isPerifRegion(address)){
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MemWrite w;
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w.address = address;
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w.size = size;
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@ -1119,6 +1139,12 @@ public:
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return this;
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}
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Workspace* loadBin(string path, uint32_t offset){
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loadBinImpl(path,&mem, offset);
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loadBinImpl(path,&riscvRef.mem, offset);
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return this;
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}
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Workspace* setCyclesPerSecond(double value){
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cyclesPerSecond = value;
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return this;
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@ -1135,24 +1161,40 @@ public:
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return this;
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}
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void iBusAccess(uint32_t addr, uint32_t *data, bool *error) {
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virtual bool isPerifRegion(uint32_t addr) { return false; }
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virtual void iBusAccess(uint32_t addr, uint32_t *data, bool *error) {
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if(addr % 4 != 0) {
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//cout << "Warning, unaligned IBusAccess : " << addr << endl;
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// fail();
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cout << "Warning, unaligned IBusAccess : " << addr << endl;
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fail();
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}
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*data = ( (mem[addr + 0] << 0)
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| (mem[addr + 1] << 8)
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| (mem[addr + 2] << 16)
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| (mem[addr + 3] << 24));
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*error = addr == 0xF00FFF60u;
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iBusAccessPatch(addr,data,error);
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*error = false;
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}
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virtual void iBusAccessPatch(uint32_t addr, uint32_t *data, bool *error){}
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virtual void dBusAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error) {
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assertEq(addr % (1 << size), 0);
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*error = addr == 0xF00FFF60u;
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if(isPerifRegion(addr)){
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if(wr){
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CpuRef::MemWrite w;
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w.address = addr;
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w.size = 1 << size;
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w.data = *data;
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riscvRef.periphWrites.push(w);
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} else {
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CpuRef::MemRead r;
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r.address = addr;
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r.size = 1 << size;
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r.data = *data;
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r.error = *error;
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riscvRef.periphRead.push(r);
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}
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} else {
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if(wr){
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memTraces <<
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#ifdef TRACE_WITH_TIME
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@ -1169,41 +1211,6 @@ public:
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*mem.get(addr + b) = *data >> (offset*8);
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}
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switch(addr){
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case 0xF0010000u: {
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cout << mem[0xF0010000u];
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logTraces << (char)mem[0xF0010000u];
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break;
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}
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#ifdef EXTERNAL_INTERRUPT
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case 0xF0011000u: top->externalInterrupt = *data & 1; break;
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#endif
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#ifdef SUPERVISOR
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case 0xF0012000u: top->externalInterruptS = *data & 1; break;
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#endif
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#ifdef CSR
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case 0xF0013000u: top->softwareInterrupt = *data & 1; break;
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#endif
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case 0xF00FFF00u: {
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cout << mem[0xF00FFF00u];
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logTraces << (char)mem[0xF00FFF00u];
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break;
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}
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#ifndef DEBUG_PLUGIN_EXTERNAL
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case 0xF00FFF20u:
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if(*data == 0)
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pass();
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else
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fail();
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break;
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case 0xF00FFF24u:
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cout << "TEST ERROR CODE " << *data << endl;
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fail();
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break;
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#endif
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case 0xF00FFF48u: mTimeCmp = (mTimeCmp & 0xFFFFFFFF00000000) | *data;break;
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case 0xF00FFF4Cu: mTimeCmp = (mTimeCmp & 0x00000000FFFFFFFF) | (((uint64_t)*data) << 32); /*cout << "mTimeCmp <= " << mTimeCmp << endl; */break;
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}
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}else{
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*data = VL_RANDOM_I(32);
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for(uint32_t b = 0;b < (1 << size);b++){
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@ -1211,19 +1218,6 @@ public:
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*data &= ~(0xFF << (offset*8));
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*data |= mem[addr + b] << (offset*8);
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}
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switch(addr){
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case 0xF00FFF10u:
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*data = mTime;
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#ifdef REF_TIME
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mTime += 100000;
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#endif
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break;
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case 0xF00FFF40u: *data = mTime; break;
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case 0xF00FFF44u: *data = mTime >> 32; break;
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case 0xF00FFF48u: *data = mTimeCmp; break;
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case 0xF00FFF4Cu: *data = mTimeCmp >> 32; break;
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case 0xF0010004u: *data = ~0; break;
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}
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memTraces <<
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#ifdef TRACE_WITH_TIME
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(currentTime
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@ -1235,24 +1229,26 @@ public:
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" : READ mem" << (1 << size) << "[" << addr << "] = " << *data << endl;
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}
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}
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}
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// void periphAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error){
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// if(wr){
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// CpuRef::MemWrite w;
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// w.address = addr;
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// w.size = 1 << size;
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// w.data = *data;
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// riscvRef.periphWrites.push(w);
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// } else {
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// CpuRef::MemRead r;
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// r.address = addr;
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// r.size = 1 << size;
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// r.data = *data;
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// r.error = *error;
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// riscvRef.periphRead.push(r);
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// }
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// }
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if((addr & 0xF0000000) == 0xF0000000){
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if(wr){
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CpuRef::MemWrite w;
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w.address = addr;
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w.size = 1 << size;
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w.data = *data;
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riscvRef.periphWrites.push(w);
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} else {
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CpuRef::MemRead r;
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r.address = addr;
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r.size = 1 << size;
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r.data = *data;
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r.error = *error;
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riscvRef.periphRead.push(r);
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}
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}
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}
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virtual void postReset() {}
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virtual void checks(){}
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virtual void pass(){ throw success();}
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@ -1266,6 +1262,7 @@ public:
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}
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Workspace* run(uint64_t timeout = 5000){
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// cout << "Start " << name << endl;
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if(timeout == 0) timeout = 0x7FFFFFFFFFFFFFFF;
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currentTime = 4;
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// init trace dump
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@ -1507,6 +1504,91 @@ public:
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};
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class WorkspaceRegression : public Workspace {
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public:
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WorkspaceRegression(string name) : Workspace(name){
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}
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virtual bool isPerifRegion(uint32_t addr) { return (addr & 0xF0000000) == 0xF0000000;}
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virtual void iBusAccess(uint32_t addr, uint32_t *data, bool *error){
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Workspace::iBusAccess(addr,data,error);
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*error = addr == 0xF00FFF60u;
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}
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virtual void dBusAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error) {
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if(wr){
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switch(addr){
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case 0xF0010000u: {
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cout << (char)*data;
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logTraces << (char)*data;
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break;
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}
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#ifdef EXTERNAL_INTERRUPT
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case 0xF0011000u: top->externalInterrupt = *data & 1; break;
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#endif
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#ifdef SUPERVISOR
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case 0xF0012000u: top->externalInterruptS = *data & 1; break;
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#endif
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#ifdef CSR
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case 0xF0013000u: top->softwareInterrupt = *data & 1; break;
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#endif
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case 0xF00FFF00u: {
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cout << (char)*data;
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logTraces << (char)*data;
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break;
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}
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#ifndef DEBUG_PLUGIN_EXTERNAL
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case 0xF00FFF20u:
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if(*data == 0)
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pass();
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else
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fail();
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break;
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case 0xF00FFF24u:
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cout << "TEST ERROR CODE " << *data << endl;
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fail();
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break;
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#endif
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case 0xF00FFF48u: mTimeCmp = (mTimeCmp & 0xFFFFFFFF00000000) | *data;break;
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case 0xF00FFF4Cu: mTimeCmp = (mTimeCmp & 0x00000000FFFFFFFF) | (((uint64_t)*data) << 32); /*cout << "mTimeCmp <= " << mTimeCmp << endl; */break;
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}
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}else{
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switch(addr){
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case 0xF00FFF10u:
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*data = mTime;
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#ifdef REF_TIME
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mTime += 100000;
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#endif
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break;
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case 0xF00FFF40u: *data = mTime; break;
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case 0xF00FFF44u: *data = mTime >> 32; break;
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case 0xF00FFF48u: *data = mTimeCmp; break;
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case 0xF00FFF4Cu: *data = mTimeCmp >> 32; break;
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case 0xF0010004u: *data = ~0; break;
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}
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memTraces <<
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#ifdef TRACE_WITH_TIME
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(currentTime
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#ifdef REF
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-2
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#endif
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) <<
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#endif
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" : READ mem" << (1 << size) << "[" << addr << "] = " << *data << endl;
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}
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*error = addr == 0xF00FFF60u;
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Workspace::dBusAccess(addr,wr,size,mask,data,error);
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}
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};
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#ifdef IBUS_SIMPLE
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class IBusSimple : public SimElement{
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@ -2407,13 +2489,13 @@ uint32_t regFileWriteRefArray[][2] = {
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testA2ReagFileWriteRef
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};
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class TestA : public Workspace{
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class TestA : public WorkspaceRegression{
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public:
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uint32_t regFileWriteRefIndex = 0;
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TestA() : Workspace("testA") {
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TestA() : WorkspaceRegression("testA") {
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loadHex("../../resources/hex/testA.hex");
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}
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@ -2431,13 +2513,13 @@ public:
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}
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};
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class TestX28 : public Workspace{
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class TestX28 : public WorkspaceRegression{
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public:
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uint32_t refIndex = 0;
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uint32_t *ref;
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uint32_t refSize;
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TestX28(string name, uint32_t *ref, uint32_t refSize) : Workspace(name) {
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TestX28(string name, uint32_t *ref, uint32_t refSize) : WorkspaceRegression(name) {
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this->ref = ref;
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this->refSize = refSize;
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loadHex("../../resources/hex/" + name + ".hex");
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@ -2457,9 +2539,9 @@ public:
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};
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class RiscvTest : public Workspace{
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class RiscvTest : public WorkspaceRegression{
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public:
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RiscvTest(string name) : Workspace(name) {
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RiscvTest(string name) : WorkspaceRegression(name) {
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loadHex("../../resources/hex/" + name + ".hex");
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bootAt(0x800000bcu);
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}
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|
|
@ -2494,16 +2576,17 @@ public:
|
|||
}
|
||||
}
|
||||
|
||||
virtual void iBusAccessPatch(uint32_t addr, uint32_t *data, bool *error){
|
||||
virtual void iBusAccess(uint32_t addr, uint32_t *data, bool *error){
|
||||
WorkspaceRegression::iBusAccess(addr,data,error);
|
||||
if(*data == 0x0ff0000f) *data = 0x00000013;
|
||||
if(*data == 0x00000073) *data = 0x00000013;
|
||||
}
|
||||
};
|
||||
#endif
|
||||
class Dhrystone : public Workspace{
|
||||
class Dhrystone : public WorkspaceRegression{
|
||||
public:
|
||||
string hexName;
|
||||
Dhrystone(string name,string hexName,bool iStall, bool dStall) : Workspace(name) {
|
||||
Dhrystone(string name,string hexName,bool iStall, bool dStall) : WorkspaceRegression(name) {
|
||||
setIStall(iStall);
|
||||
setDStall(dStall);
|
||||
withRiscvRef();
|
||||
|
|
@ -2543,12 +2626,12 @@ public:
|
|||
}
|
||||
};
|
||||
|
||||
class Compliance : public Workspace{
|
||||
class Compliance : public WorkspaceRegression{
|
||||
public:
|
||||
string name;
|
||||
ofstream out32;
|
||||
int out32Counter = 0;
|
||||
Compliance(string name) : Workspace(name) {
|
||||
Compliance(string name) : WorkspaceRegression(name) {
|
||||
withRiscvRef();
|
||||
loadHex("../../resources/hex/" + name + ".elf.hex");
|
||||
out32.open (name + ".out32");
|
||||
|
|
@ -2558,12 +2641,11 @@ public:
|
|||
|
||||
|
||||
virtual void dBusAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error) {
|
||||
Workspace::dBusAccess(addr,wr,size,mask,data,error);
|
||||
if(wr && addr == 0xF00FFF2C){
|
||||
out32 << hex << setw(8) << std::setfill('0') << *data << dec;
|
||||
if(++out32Counter % 4 == 0) out32 << "\n";
|
||||
*error = 0;
|
||||
}
|
||||
WorkspaceRegression::dBusAccess(addr,wr,size,mask,data,error);
|
||||
}
|
||||
|
||||
virtual void checks(){
|
||||
|
|
@ -2621,7 +2703,7 @@ public:
|
|||
#define RISCV_SPINAL_FLAGS_RESET_CLEAR 1<<24
|
||||
#define RISCV_SPINAL_FLAGS_HALT_CLEAR 1<<25
|
||||
|
||||
class DebugPluginTest : public Workspace{
|
||||
class DebugPluginTest : public WorkspaceRegression{
|
||||
public:
|
||||
pthread_t clientThreadId;
|
||||
char buffer[1024];
|
||||
|
|
@ -2761,7 +2843,7 @@ public:
|
|||
}
|
||||
|
||||
|
||||
DebugPluginTest() : Workspace("DebugPluginTest") {
|
||||
DebugPluginTest() : WorkspaceRegression("DebugPluginTest") {
|
||||
loadHex("../../resources/hex/debugPlugin.hex");
|
||||
pthread_create(&clientThreadId, NULL, &clientThreadWrapper, this);
|
||||
noInstructionReadCheck();
|
||||
|
|
@ -2779,6 +2861,28 @@ public:
|
|||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef LITEX
|
||||
class LitexSoC : public Workspace{
|
||||
public:
|
||||
|
||||
LitexSoC(string name) : Workspace(name) {
|
||||
|
||||
}
|
||||
|
||||
virtual bool isPerifRegion(uint32_t addr) { return (addr & 0xF0000000) == 0xB0000000 || (addr & 0xF0000000) == 0xE0000000;}
|
||||
|
||||
|
||||
virtual void dBusAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error) {
|
||||
switch(addr){
|
||||
//TODO Emulate peripherals here
|
||||
}
|
||||
|
||||
Workspace::dBusAccess(addr,wr,size,mask,data,error);
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
string riscvTestMain[] = {
|
||||
//"rv32ui-p-simple",
|
||||
"rv32ui-p-lui",
|
||||
|
|
@ -3045,17 +3149,30 @@ int main(int argc, char **argv, char **env) {
|
|||
printf("BOOT\n");
|
||||
timespec startedAt = timer_start();
|
||||
|
||||
|
||||
#ifdef LITEX
|
||||
LitexSoC("linux")
|
||||
.withRiscvRef()
|
||||
->loadBin(VMLINUX, 0xc0000000)
|
||||
->loadBin(RAMDISK, 0xc2000000)
|
||||
->setIStall(false) //TODO It currently improve speed but should be removed later
|
||||
->setDStall(false)
|
||||
->bootAt(0xc0000000)
|
||||
->run(0);
|
||||
return 1;
|
||||
#endif
|
||||
|
||||
// #ifdef MMU
|
||||
// redo(REDO,Workspace("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
// redo(REDO,WorkspaceRegression("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
// #endif
|
||||
// redo(REDO,Workspace("deleg").withRiscvRef()->loadHex("../raw/deleg/build/deleg.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
// redo(REDO,WorkspaceRegression("deleg").withRiscvRef()->loadHex("../raw/deleg/build/deleg.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
// return 0;
|
||||
|
||||
for(int idx = 0;idx < 1;idx++){
|
||||
|
||||
#if defined(DEBUG_PLUGIN_EXTERNAL) || defined(RUN_HEX)
|
||||
{
|
||||
Workspace w("run");
|
||||
WorkspaceRegression w("run");
|
||||
#ifdef RUN_HEX
|
||||
//w.loadHex("/home/spinalvm/hdl/zephyr/zephyrSpinalHdl/samples/synchronization/build/zephyr/zephyr.hex");
|
||||
w.loadHex(RUN_HEX);
|
||||
|
|
@ -3154,10 +3271,10 @@ int main(int argc, char **argv, char **env) {
|
|||
// #endif
|
||||
|
||||
#ifdef MMU
|
||||
redo(REDO,Workspace("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
redo(REDO,WorkspaceRegression("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
#endif
|
||||
#ifdef SUPERVISOR
|
||||
redo(REDO,Workspace("deleg").withRiscvRef()->loadHex("../raw/deleg/build/deleg.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
redo(REDO,WorkspaceRegression("deleg").withRiscvRef()->loadHex("../raw/deleg/build/deleg.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG_PLUGIN
|
||||
|
|
@ -3166,16 +3283,16 @@ int main(int argc, char **argv, char **env) {
|
|||
#endif
|
||||
|
||||
#ifdef CUSTOM_SIMD_ADD
|
||||
redo(REDO,Workspace("custom_simd_add").loadHex("../custom/simd_add/build/custom_simd_add.hex")->bootAt(0x00000000u)->run(50e3););
|
||||
redo(REDO,WorkspaceRegression("custom_simd_add").loadHex("../custom/simd_add/build/custom_simd_add.hex")->bootAt(0x00000000u)->run(50e3););
|
||||
#endif
|
||||
|
||||
#ifdef CUSTOM_CSR
|
||||
redo(REDO,Workspace("custom_csr").loadHex("../custom/custom_csr/build/custom_csr.hex")->bootAt(0x00000000u)->run(50e3););
|
||||
redo(REDO,WorkspaceRegression("custom_csr").loadHex("../custom/custom_csr/build/custom_csr.hex")->bootAt(0x00000000u)->run(50e3););
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef ATOMIC
|
||||
redo(REDO,Workspace("atomic").loadHex("../custom/atomic/build/atomic.hex")->bootAt(0x00000000u)->run(10e3););
|
||||
redo(REDO,WorkspaceRegression("atomic").loadHex("../custom/atomic/build/atomic.hex")->bootAt(0x00000000u)->run(10e3););
|
||||
#endif
|
||||
|
||||
#ifdef DHRYSTONE
|
||||
|
|
@ -3206,22 +3323,22 @@ int main(int argc, char **argv, char **env) {
|
|||
#ifdef SEED
|
||||
srand48(SEED);
|
||||
#endif
|
||||
//redo(1,Workspace("freeRTOS_demo").loadHex("../../resources/hex/freeRTOS_demo.hex")->bootAt(0x80000000u)->run(100e6);)
|
||||
//redo(1,WorkspaceRegression("freeRTOS_demo").loadHex("../../resources/hex/freeRTOS_demo.hex")->bootAt(0x80000000u)->run(100e6);)
|
||||
vector <std::function<void()>> tasks;
|
||||
|
||||
/*for(int redo = 0;redo < 4;redo++)*/{
|
||||
for(const string &name : freeRtosTests){
|
||||
tasks.push_back([=]() { Workspace(name + "_rv32i_O0").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32i_O0.hex")->bootAt(0x80000000u)->run(4e6*15);});
|
||||
tasks.push_back([=]() { Workspace(name + "_rv32i_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32i_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
|
||||
tasks.push_back([=]() { WorkspaceRegression(name + "_rv32i_O0").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32i_O0.hex")->bootAt(0x80000000u)->run(4e6*15);});
|
||||
tasks.push_back([=]() { WorkspaceRegression(name + "_rv32i_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32i_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
|
||||
#ifdef COMPRESSED
|
||||
tasks.push_back([=]() { Workspace(name + "_rv32ic_O0").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32ic_O0.hex")->bootAt(0x80000000u)->run(5e6*15);});
|
||||
tasks.push_back([=]() { Workspace(name + "_rv32ic_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32ic_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
|
||||
tasks.push_back([=]() { WorkspaceRegression(name + "_rv32ic_O0").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32ic_O0.hex")->bootAt(0x80000000u)->run(5e6*15);});
|
||||
tasks.push_back([=]() { WorkspaceRegression(name + "_rv32ic_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32ic_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
|
||||
#endif
|
||||
#if defined(MUL) && defined(DIV)
|
||||
#ifdef COMPRESSED
|
||||
tasks.push_back([=]() { Workspace(name + "_rv32imac_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32imac_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
|
||||
tasks.push_back([=]() { WorkspaceRegression(name + "_rv32imac_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32imac_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
|
||||
#else
|
||||
tasks.push_back([=]() { Workspace(name + "_rv32im_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32im_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
|
||||
tasks.push_back([=]() { WorkspaceRegression(name + "_rv32im_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32im_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -48,6 +48,13 @@ else
|
|||
endif
|
||||
|
||||
|
||||
|
||||
ifeq ($(LITEX),yes)
|
||||
ADDCFLAGS += -CFLAGS -DLITEX
|
||||
ADDCFLAGS += -CFLAGS -DVMLINUX='\"$(VMLINUX)\"'
|
||||
ADDCFLAGS += -CFLAGS -DRAMDISK='\"$(RAMDISK)\"'
|
||||
endif
|
||||
|
||||
ifneq ($(shell grep timerInterrupt ../../../../VexRiscv.v -w),)
|
||||
ADDCFLAGS += -CFLAGS -DTIMER_INTERRUPT
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue