Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Better doc about iorange

This commit is contained in:
Dolu1990 2021-06-02 10:27:46 +02:00
parent 0272d66971
commit 6cde5f9315
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
README.md
View File

@ -1072,6 +1072,11 @@ stage before jumping to mtvec.
Static memory translator plugin which allows to specify which range of the memory addresses is I/O mapped and shouldn't be cached. Static memory translator plugin which allows to specify which range of the memory addresses is I/O mapped and shouldn't be cached.
| Parameters | type | description |
| ------ | ----------- | ------ |
| ioRange | UInt => Bool | Function reference which eat an address and return true if the address should be uncached. ex : ioRange= _(31 downto 28) === 0xF => all 0xFXXXXXXX will be uncached|
#### MmuPlugin #### MmuPlugin
Hardware refilled MMU implementation. Allows other plugins such as DBusCachedPlugin/IBusCachedPlugin to instanciate memory address translation ports. Each port has a small dedicated Hardware refilled MMU implementation. Allows other plugins such as DBusCachedPlugin/IBusCachedPlugin to instanciate memory address translation ports. Each port has a small dedicated