Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Improve CSR FMax

This commit is contained in:
Charles Papon 2019-09-16 13:53:55 +02:00
parent b65ef189eb
commit 6ed41f7361
1 changed files with 7 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -945,9 +945,14 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
val readData = B(0, 32 bits)
val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE)
val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE)
val writeEnable = writeInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// && readDataRegValid
val readEnable = readInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// && !readDataRegValid
val writeEnable = writeInstruction && ! blockedBySideEffects // && readDataRegValid
val readEnable = readInstruction && ! blockedBySideEffects // && !readDataRegValid
//arbitration.isStuckByOthers, in case of the hazardPlugin is in the executeStage
val hazardStage = service(classOf[RegFileService]).readStage()
if(hazardStage == execute) when (arbitration.isStuckByOthers){
writeEnable := False
readEnable := False
}
// def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT