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Fetcher.decompressor ensure that the decoded instruction do not mutate when the pipeline is stalled (fix FPU cmd fork for rvc without injector stage)

This commit is contained in:
Dolu1990 2021-03-25 14:13:12 +01:00
parent 21c91c6b70
commit 6f481f51ef
1 changed files with 9 additions and 2 deletions
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11
src/main/scala/vexriscv/plugin/Fetcher.scala
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@ -256,10 +256,17 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
val throw2Bytes = throw2BytesReg || input.pc(1)
val unaligned = throw2Bytes || bufferValid
def aligned = !unaligned
//Latch and patches are there to ensure that the decoded instruction do not mutate while being halted and unscheduled to ensure FpuPlugin cmd fork from consistancy
val bufferValidLatch = RegNextWhen(bufferValid, input.valid)
val throw2BytesLatch = RegNextWhen(throw2Bytes, input.valid)
val bufferValidPatched = input.valid ? bufferValid | bufferValidLatch
val throw2BytesPatched = input.valid ? throw2Bytes | throw2BytesLatch
val raw = Mux(
sel = bufferValid,
sel = bufferValidPatched,
whenTrue = input.rsp.inst(15 downto 0) ## bufferData,
whenFalse = input.rsp.inst(31 downto 16) ## (throw2Bytes ? input.rsp.inst(31 downto 16) | input.rsp.inst(15 downto 0))
whenFalse = input.rsp.inst(31 downto 16) ## (throw2BytesPatched ? input.rsp.inst(31 downto 16) | input.rsp.inst(15 downto 0))
)
val isRvc = raw(1 downto 0) =/= 3
val decompressed = RvcDecompressor(raw(15 downto 0), pipeline.config.withRvf, pipeline.config.withRvd)