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README.md
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README.md
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WIP
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This repository host an RISC-V implementation written in SpinalHDL. There is some specs :
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- RV32IM instruction set
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- Interrupts and exception handling with the Machine mode from the riscv-privileged-v1.9.1 specification.
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- Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
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- 1.17 DMIPS/Mhz with all extension
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- Optimized for FPGA
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- Optional MUL/DIV/REM extension
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- Two implementation of shift instructions, Single cycle / shiftNumber cycle
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- Each stage could have bypass or interlock hazard logic
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- FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV
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The hardware description of this CPU is done by using an very software oriented approach
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(without any overhead in the generated hardware). There is a list of software concepts used :
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- There is very few fixed things. Nearly everything is plugin based. The PC manager is a plugin, the register file is a plugin, the hazard controller is a plugin ...
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- There is an automatic a tool which allow plugins to insert data in the pipeline at a given stage, and allow other plugins to read it in another stages through automatic pipelining.
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- There is an service system which provide a very dynamic framework. As instance, a plugin could provide an exception service which could then be used by others plugins to emit exceptions from the pipeline.
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## Plugin structure
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```scala
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//Define an signal name/type which could be used in the pipeline
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object ALU_ENABLE extends Stageable(Bool)
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object ALU_OP extends Stageable(Bits(2 bits)) // ADD, SUB, AND, OR
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object ALU_SRC1 extends Stageable(UInt(32 bits))
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object ALU_SRC2 extends Stageable(UInt(32 bits))
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object ALU_RESULT extends Stageable(UInt(32 bits))
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class AluPlugin() extends Plugin[VexRiscv]{
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override def setup(pipeline: VexRiscv): Unit = {
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import pipeline.config._
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//Do some setups as for example specifying some instruction decoding by using the Decoding service
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val decoderService = pipeline.service(classOf[DecoderService])
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decoderService.addDefault(ALU_ENABLE,False)
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decodingService.add(List(
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//.....
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))
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}
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline._
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execute plug new Area {
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import execute._
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//Add some logic in the execute stage
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insert(ALU_RESULT) := input(ALU_OP).mux(
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B"00" -> input(ALU_SRC1) + input(ALU_SRC2),
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B"01" -> input(ALU_SRC1) - input(ALU_SRC2),
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B"10" -> input(ALU_SRC1) & input(ALU_SRC2),
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B"11" -> input(ALU_SRC1) | input(ALU_SRC2),
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)
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}
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writeBack plug new Area {
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import writeBack._
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//Add some logic in the execute stage
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when(input(ALU_ENABLE)){
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input(REGFILE_WRITE_DATA) := input(ALU_RESULT)
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}
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}
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}
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}
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```
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