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VexRiscv
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CsrPlugin now support utime csr to avoid emulation

This commit is contained in:
Dolu1990 2020-06-05 10:35:50 +02:00
parent 3dafe8708b
commit 71760ea372
2 changed files with 13 additions and 2 deletions
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7
src/main/scala/vexriscv/Riscv.scala
View File

@ -159,7 +159,10 @@ object Riscv{
def UCYCLE = 0xC00 // UR Machine ucycle counter.
def UCYCLEH = 0xC80
def UCYCLE = 0xC00 // UR Machine ucycle counter.
def UCYCLEH = 0xC80
def UTIME = 0xC01 // rdtime
def UTIMEH = 0xC81
}
}

8
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -66,6 +66,7 @@ case class CsrPluginConfig(
scycleAccess : CsrAccess = CsrAccess.NONE,
sinstretAccess : CsrAccess = CsrAccess.NONE,
satpAccess : CsrAccess = CsrAccess.NONE,
utimeAccess :CsrAccess = CsrAccess.NONE,
medelegAccess : CsrAccess = CsrAccess.NONE,
midelegAccess : CsrAccess = CsrAccess.NONE,
withExternalMhartid : Boolean = false,
@ -390,6 +391,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
var thirdPartyWake : Bool = null
var inWfi : Bool = null
var externalMhartId : UInt = null
var utime : UInt = null
override def askWake(): Unit = thirdPartyWake := True
@ -520,6 +522,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
pipeline.update(MPP, UInt(2 bits))
if(withExternalMhartid) externalMhartId = in UInt(mhartidWidth bits)
if(utimeAccess != CsrAccess.NONE) utime = in UInt(64 bits) setName("utime")
}
def inhibateInterrupts() : Unit = allowInterrupts := False
@ -634,6 +637,11 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
ucycleAccess(CSR.UCYCLE, mcycle(31 downto 0))
ucycleAccess(CSR.UCYCLEH, mcycle(63 downto 32))
if(utimeAccess != CsrAccess.NONE) {
utimeAccess(CSR.UTIME, utime(31 downto 0))
utimeAccess(CSR.UTIMEH, utime(63 downto 32))
}
pipeline(MPP) := mstatus.MPP
}