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VexRiscv
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Fix coremark binaries (no csr)

This commit is contained in:
Charles Papon 2019-04-19 18:28:46 +02:00
parent a496638c72
commit 728a5ff20f
3 changed files with 8 additions and 7 deletions
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9
.travis.yml
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@ -23,10 +23,10 @@ jdk:
env: env:
- VEXRISCV_REGRESSION_CONFIG_COUNT=0 - VEXRISCV_REGRESSION_CONFIG_COUNT=0
- VEXRISCV_REGRESSION_CONFIG_COUNT=5 # - VEXRISCV_REGRESSION_CONFIG_COUNT=5
- VEXRISCV_REGRESSION_CONFIG_COUNT=5 #- VEXRISCV_REGRESSION_CONFIG_COUNT=5
- VEXRISCV_REGRESSION_CONFIG_COUNT=5 #- VEXRISCV_REGRESSION_CONFIG_COUNT=5
- VEXRISCV_REGRESSION_CONFIG_COUNT=5 #- VEXRISCV_REGRESSION_CONFIG_COUNT=5
before_install: before_install:
# JDK fix # JDK fix
@ -64,3 +64,4 @@ cache:
directories: directories:
- $HOME/.ivy2/cache - $HOME/.ivy2/cache
- $HOME/.sbt/boot/ - $HOME/.sbt/boot/
- verilator-4.012

4
src/test/cpp/regression/main.cpp
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@ -1821,7 +1821,7 @@ public:
virtual void preCycle(){ virtual void preCycle(){
if (top->iBusTc_enable) { if (top->iBusTc_enable) {
if((top->iBusTc_address & 0x70000000) != 0 || (top->iBusTc_address & 0x20) == 0){ if((top->iBusTc_address & 0x70000000) != 0){
printf("IBusTc access out of range\n"); printf("IBusTc access out of range\n");
ws->fail(); ws->fail();
} }
@ -1921,7 +1921,7 @@ public:
top->iBus_rsp_valid = 0; top->iBus_rsp_valid = 0;
if(pendingCount != 0 && (!ws->iStall || VL_RANDOM_I(7) < 100)){ if(pendingCount != 0 && (!ws->iStall || VL_RANDOM_I(7) < 100)){
#ifdef IBUS_TC #ifdef IBUS_TC
if((address & 0x70000000) == 0 && (address & 0x20) != 0){ if((address & 0x70000000) == 0){
printf("IBUS_CACHED access out of range\n"); printf("IBUS_CACHED access out of range\n");
ws->fail(); ws->fail();
} }

2
src/test/scala/vexriscv/TestIndividualFeatures.scala
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@ -331,7 +331,7 @@ class IBusDimension extends VexRiscvDimension("IBus") {
twoCycleCache = twoCycleCache twoCycleCache = twoCycleCache
) )
) )
if(tighlyCoupled) p.newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5))) if(tighlyCoupled) p.newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0))
config.plugins += p config.plugins += p
} }
override def instructionAnticipatedOk() = !twoCycleCache || ((!twoCycleRam || wayCount == 1) && !compressed) override def instructionAnticipatedOk() = !twoCycleCache || ((!twoCycleRam || wayCount == 1) && !compressed)