Fix coremark binaries (no csr)

.travis.yml

@@ -23,10 +23,10 @@ jdk:
 
 env:
   - VEXRISCV_REGRESSION_CONFIG_COUNT=0
-  - VEXRISCV_REGRESSION_CONFIG_COUNT=5
-  - VEXRISCV_REGRESSION_CONFIG_COUNT=5
-  - VEXRISCV_REGRESSION_CONFIG_COUNT=5
-  - VEXRISCV_REGRESSION_CONFIG_COUNT=5
+  #  - VEXRISCV_REGRESSION_CONFIG_COUNT=5
+  #- VEXRISCV_REGRESSION_CONFIG_COUNT=5
+  #- VEXRISCV_REGRESSION_CONFIG_COUNT=5
+  #- VEXRISCV_REGRESSION_CONFIG_COUNT=5
 
 before_install:
   # JDK fix
@@ -64,3 +64,4 @@ cache:
   directories:
     - $HOME/.ivy2/cache
     - $HOME/.sbt/boot/
+    - verilator-4.012

src/test/cpp/regression/main.cpp

@@ -1821,7 +1821,7 @@ public:
 
 	virtual void preCycle(){
 		if (top->iBusTc_enable) {
-		    if((top->iBusTc_address & 0x70000000) != 0 || (top->iBusTc_address & 0x20) == 0){
+		    if((top->iBusTc_address & 0x70000000) != 0){
 		        printf("IBusTc access out of range\n");
 		        ws->fail();
 		    }
@@ -1921,7 +1921,7 @@ public:
 		top->iBus_rsp_valid = 0;
 		if(pendingCount != 0 && (!ws->iStall || VL_RANDOM_I(7) < 100)){
 		    #ifdef IBUS_TC
-            if((address & 0x70000000) == 0 && (address & 0x20) != 0){
+            if((address & 0x70000000) == 0){
                 printf("IBUS_CACHED access out of range\n");
                 ws->fail();
             }

src/test/scala/vexriscv/TestIndividualFeatures.scala

@@ -331,7 +331,7 @@ class IBusDimension extends VexRiscvDimension("IBus") {
               twoCycleCache = twoCycleCache
             )
           )
-          if(tighlyCoupled) p.newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5)))
+          if(tighlyCoupled) p.newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0))
           config.plugins += p
         }
         override def instructionAnticipatedOk() = !twoCycleCache || ((!twoCycleRam || wayCount == 1) && !compressed)