Add VexRiscvSmpCluster, seem to work on simple case
This commit is contained in:
Dolu1990
parent
b9ceabf128
commit
73c21177e5
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package vexriscv.demo.smp
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import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.bmb.sim.BmbMemoryAgent
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import spinal.lib.bus.bmb.{Bmb, BmbArbiter, BmbDecoder, BmbExclusiveMonitor, BmbInvalidateMonitor, BmbParameter}
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.com.jtag.sim.JtagTcp
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import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCacheConfig}
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import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin}
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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case class VexRiscvSmpClusterParameter( cpuConfigs : Seq[VexRiscvConfig])
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case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
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debugClockDomain : ClockDomain) extends Component{
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val dBusParameter = p.cpuConfigs.head.plugins.find(_.isInstanceOf[DBusCachedPlugin]).get.asInstanceOf[DBusCachedPlugin].config.getBmbParameter()
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val dBusArbiterParameter = dBusParameter.copy(sourceWidth = log2Up(p.cpuConfigs.size))
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val exclusiveMonitorParameter = dBusArbiterParameter
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val invalidateMonitorParameter = BmbExclusiveMonitor.outputParameter(exclusiveMonitorParameter)
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val dMemParameter = BmbInvalidateMonitor.outputParameter(invalidateMonitorParameter)
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val iBusParameter = p.cpuConfigs.head.plugins.find(_.isInstanceOf[IBusCachedPlugin]).get.asInstanceOf[IBusCachedPlugin].config.getBmbParameter()
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val iBusArbiterParameter = iBusParameter.copy(sourceWidth = log2Up(p.cpuConfigs.size))
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val iMemParameter = iBusArbiterParameter
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val io = new Bundle {
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val dMem = master(Bmb(dMemParameter))
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val iMem = master(Bmb(iMemParameter))
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val timerInterrupts = in Bits(p.cpuConfigs.size bits)
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val externalInterrupts = in Bits(p.cpuConfigs.size bits)
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val externalSupervisorInterrupts = in Bits(p.cpuConfigs.size bits)
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val jtag = slave(Jtag())
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val debugReset = out Bool()
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}
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val cpus = for((cpuConfig, cpuId) <- p.cpuConfigs.zipWithIndex) yield new Area{
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var iBus : Bmb = null
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var dBus : Bmb = null
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cpuConfig.plugins.foreach {
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case plugin: DebugPlugin => debugClockDomain{
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plugin.debugClockDomain = debugClockDomain
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}
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case _ =>
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}
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val core = new VexRiscv(cpuConfig)
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core.plugins.foreach {
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case plugin: IBusCachedPlugin => iBus = plugin.iBus.toBmb()
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case plugin: DBusCachedPlugin => dBus = plugin.dBus.toBmb()
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case plugin: CsrPlugin => {
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plugin.externalInterrupt := io.externalInterrupts(cpuId)
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plugin.timerInterrupt := io.timerInterrupts(cpuId)
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if (plugin.config.supervisorGen) plugin.externalInterruptS := io.externalSupervisorInterrupts(cpuId)
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}
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case plugin: DebugPlugin => debugClockDomain{
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io.debugReset := RegNext(plugin.io.resetOut)
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io.jtag <> plugin.io.bus.fromJtag()
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}
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case _ =>
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}
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}
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val dBusArbiter = BmbArbiter(
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p = dBusArbiterParameter,
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portCount = cpus.size,
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pendingRspMax = 64,
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lowerFirstPriority = false,
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inputsWithInv = cpus.map(_ => true),
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inputsWithSync = cpus.map(_ => true),
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pendingInvMax = 16
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)
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(dBusArbiter.io.inputs, cpus).zipped.foreach(_ << _.dBus)
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val exclusiveMonitor = BmbExclusiveMonitor(
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inputParameter = exclusiveMonitorParameter,
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pendingWriteMax = 64
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)
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exclusiveMonitor.io.input << dBusArbiter.io.output
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val invalidateMonitor = BmbInvalidateMonitor(
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inputParameter = invalidateMonitorParameter,
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pendingInvMax = 16
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)
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invalidateMonitor.io.input << exclusiveMonitor.io.output
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io.dMem << invalidateMonitor.io.output
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val iBusArbiter = BmbArbiter(
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p = iBusArbiterParameter,
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portCount = cpus.size,
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pendingRspMax = 64,
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lowerFirstPriority = false,
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inputsWithInv = cpus.map(_ => true),
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inputsWithSync = cpus.map(_ => true),
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pendingInvMax = 16
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)
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(iBusArbiter.io.inputs, cpus).zipped.foreach(_ << _.iBus)
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io.iMem << iBusArbiter.io.output
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}
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object VexRiscvSmpClusterGen {
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def vexRiscvConfig(id : Int) = {
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val config = VexRiscvConfig(
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plugins = List(
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new MmuPlugin(
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ioRange = x => x(31 downto 28) === 0xF
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),
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//Uncomment the whole IBusSimplePlugin and comment IBusCachedPlugin if you want uncached iBus config
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// new IBusSimplePlugin(
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// resetVector = 0x80000000l,
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// cmdForkOnSecondStage = false,
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// cmdForkPersistence = false,
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// prediction = DYNAMIC_TARGET,
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// historyRamSizeLog2 = 10,
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// catchAccessFault = true,
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// compressedGen = true,
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// busLatencyMin = 1,
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// injectorStage = true,
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// memoryTranslatorPortConfig = withMmu generate MmuPortConfig(
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// portTlbSize = 4
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// )
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// ),
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//Uncomment the whole IBusCachedPlugin and comment IBusSimplePlugin if you want cached iBus config
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new IBusCachedPlugin(
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resetVector = 0x80000000l,
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compressedGen = false,
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prediction = STATIC,
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injectorStage = false,
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config = InstructionCacheConfig(
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cacheSize = 4096*1,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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asyncTagMemory = false,
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twoCycleRam = false,
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twoCycleCache = true
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// )
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),
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memoryTranslatorPortConfig = MmuPortConfig(
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portTlbSize = 4
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)
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),
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// ).newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5))),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = true,
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// catchAccessFault = true,
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// earlyInjection = false,
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// withLrSc = true,
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// memoryTranslatorPortConfig = withMmu generate MmuPortConfig(
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// portTlbSize = 4
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// )
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// ),
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new DBusCachedPlugin(
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dBusCmdMasterPipe = true,
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dBusCmdSlavePipe = true,
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dBusRspSlavePipe = true,
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config = new DataCacheConfig(
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cacheSize = 4096*1,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true,
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withLrSc = true,
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withAmo = true,
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withExclusive = true,
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withInvalidate = true
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// )
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),
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memoryTranslatorPortConfig = MmuPortConfig(
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portTlbSize = 4
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)
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),
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// new MemoryTranslatorPlugin(
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// tlbSize = 32,
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// virtualRange = _(31 downto 28) === 0xC,
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// ioRange = _(31 downto 28) === 0xF
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// ),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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new FullBarrelShifterPlugin(earlyInjection = false),
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// new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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// new HazardSimplePlugin(false, true, false, true),
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// new HazardSimplePlugin(false, false, false, false),
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new MulPlugin,
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new MulDivIterativePlugin(
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genMul = false,
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genDiv = true,
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mulUnrollFactor = 32,
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divUnrollFactor = 1
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),
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// new DivPlugin,
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new CsrPlugin(CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = false, mhartid = id)),
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// new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/*
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// CsrPluginConfig(
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// catchIllegalAccess = false,
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// mvendorid = null,
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// marchid = null,
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// mimpid = null,
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// mhartid = null,
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// misaExtensionsInit = 0,
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// misaAccess = CsrAccess.READ_ONLY,
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// mtvecAccess = CsrAccess.WRITE_ONLY,
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// mtvecInit = 0x80000020l,
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// mepcAccess = CsrAccess.READ_WRITE,
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// mscratchGen = true,
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// mcauseAccess = CsrAccess.READ_ONLY,
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// mbadaddrAccess = CsrAccess.READ_ONLY,
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// mcycleAccess = CsrAccess.NONE,
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// minstretAccess = CsrAccess.NONE,
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// ecallGen = true,
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// ebreakGen = true,
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// wfiGenAsWait = false,
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// wfiGenAsNop = true,
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// ucycleAccess = CsrAccess.NONE
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// )),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true,
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fenceiGenAsAJump = false
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),
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new YamlPlugin(s"cpu$id.yaml")
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)
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)
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if(id == 0) config.plugins += new DebugPlugin(null)
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config
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}
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def vexRiscvCluster() = VexRiscvSmpCluster(
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debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")),
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p = VexRiscvSmpClusterParameter(
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cpuConfigs = List.tabulate(4) {
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vexRiscvConfig(_)
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}
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)
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)
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def main(args: Array[String]): Unit = {
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SpinalVerilog {
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vexRiscvCluster()
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}
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}
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}
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object VexRiscvSmpClusterTest extends App{
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import spinal.core.sim._
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val simConfig = SimConfig
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simConfig.withWave
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simConfig.allOptimisation
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simConfig.addSimulatorFlag("--threads 1")
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simConfig.compile(VexRiscvSmpClusterGen.vexRiscvCluster()).doSim(seed = 42){dut =>
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dut.clockDomain.forkSimSpeedPrinter(1.0)
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dut.clockDomain.forkStimulus(10)
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dut.debugClockDomain.forkStimulus(10)
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JtagTcp(dut.io.jtag, 100)
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val ram = new BmbMemoryAgent(0x100000000l)
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ram.addPort(dut.io.iMem,0,dut.clockDomain,true)
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ram.addPort(dut.io.dMem,0,dut.clockDomain,true)
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ram.memory.loadBin(0x80000000l, "src/test/cpp/raw/smp/build/smp.bin")
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sleep(10000*10)
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simSuccess()
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}
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}
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@ -0,0 +1,5 @@
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*.map
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*.v
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*.elf
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*.o
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*.hex
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@ -0,0 +1,108 @@
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build/smp.elf: file format elf32-littleriscv
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Disassembly of section .crt_section:
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80000000 <_start>:
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80000000: f1402a73 csrr s4,mhartid
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80000004: 00000517 auipc a0,0x0
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80000008: 07850513 addi a0,a0,120 # 8000007c <test1_data>
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8000000c: 00000513 li a0,0
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80000010: 00a52023 sw a0,0(a0)
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80000014 <count_thread_start>:
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80000014: 00100513 li a0,1
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80000018: 00000597 auipc a1,0x0
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8000001c: 05c58593 addi a1,a1,92 # 80000074 <thread_count>
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80000020: 00a5a02f amoadd.w zero,a0,(a1)
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80000024 <count_thread_wait>:
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80000024: 00000417 auipc s0,0x0
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80000028: 05042403 lw s0,80(s0) # 80000074 <thread_count>
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8000002c: 0c800513 li a0,200
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80000030: 038000ef jal ra,80000068 <sleep>
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80000034: 00000497 auipc s1,0x0
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80000038: 0404a483 lw s1,64(s1) # 80000074 <thread_count>
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8000003c: fe8494e3 bne s1,s0,80000024 <count_thread_wait>
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80000040: 00000513 li a0,0
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80000044: 00952023 sw s1,0(a0)
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80000048: 0040006f j 8000004c <success>
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8000004c <success>:
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8000004c: 00800513 li a0,8
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80000050: 00052023 sw zero,0(a0)
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80000054: 0100006f j 80000064 <end>
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80000058 <failure>:
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80000058: 00c00513 li a0,12
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8000005c: 00052023 sw zero,0(a0)
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80000060: 0040006f j 80000064 <end>
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80000064 <end>:
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80000064: 0000006f j 80000064 <end>
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80000068 <sleep>:
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80000068: fff50513 addi a0,a0,-1
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8000006c: fe051ee3 bnez a0,80000068 <sleep>
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80000070: 00008067 ret
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80000074 <thread_count>:
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80000074: 0000 unimp
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...
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80000078 <shared_memory_1>:
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80000078: 0000 unimp
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...
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8000007c <test1_data>:
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8000007c: 0000000b 0xb
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80000080 <test2_data>:
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80000080: 0016 c.slli zero,0x5
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...
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80000084 <test3_data>:
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80000084: 0049 c.nop 18
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...
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80000088 <test4_data>:
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80000088: 003a c.slli zero,0xe
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...
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8000008c <test5_data>:
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8000008c: 0038 addi a4,sp,8
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...
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80000090 <test6_data>:
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80000090: 0000004b fnmsub.s ft0,ft0,ft0,ft0,rne
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80000094 <test7_data>:
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80000094: 0038 addi a4,sp,8
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...
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80000098 <test8_data>:
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80000098: 00000053 fadd.s ft0,ft0,ft0,rne
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8000009c <test9_data>:
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8000009c: 0021 c.nop 8
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...
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800000a0 <test10_data>:
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800000a0: ffffffbf 0xffffffbf
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800000a4 <test11_data>:
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800000a4: ffa9 bnez a5,7ffffffe <_start-0x2>
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800000a6: ffff 0xffff
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800000a8 <test12_data>:
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800000a8: ffc9 bnez a5,80000042 <count_thread_wait+0x1e>
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800000aa: ffff 0xffff
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800000ac <test13_data>:
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800000ac: 0004 0x4
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800000ae: ffff 0xffff
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800000b0 <test14_data>:
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800000b0: 0005 c.nop 1
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800000b2: ffff 0xffff
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@ -0,0 +1,5 @@
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PROJ_NAME=smp
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ATOMIC=yes
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include ../common/asm.mk
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@ -0,0 +1,70 @@
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#define REPORT_OFFSET 0xF0000000
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#define REPORT_THREAD_ID 0
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#define REPORT_THREAD_COUNT 1
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#define REPORT_SUCCESS 2
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#define REPORT_FAILURE 3
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#define report(reg, id) \
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li a0, id*4; \
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sw reg, 0(a0); \
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_start:
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#define HART_ID x20
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csrr HART_ID, mhartid
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la a0, test1_data
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report(a0, REPORT_THREAD_ID)
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count_thread_start:
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//Count up threads
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li a0, 1
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la a1, thread_count
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amoadd.w x0, a0, (a1)
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count_thread_wait:
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//Wait everybody
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lw s0, thread_count
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li a0, 200
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call sleep
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lw s1, thread_count
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bne s1, s0, count_thread_wait
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report(s1, REPORT_THREAD_ID)
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j success
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success:
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report(x0, REPORT_SUCCESS)
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j end
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failure:
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report(x0, REPORT_FAILURE)
|
||||
j end
|
||||
|
||||
end:
|
||||
j end
|
||||
|
||||
|
||||
sleep:
|
||||
addi a0, a0, -1
|
||||
bnez a0, sleep
|
||||
ret
|
||||
|
||||
|
||||
thread_count: .word 0
|
||||
shared_memory_1: .word 0
|
||||
|
||||
test1_data: .word 11
|
||||
test2_data: .word 22
|
||||
test3_data: .word 73
|
||||
test4_data: .word 58
|
||||
test5_data: .word 56
|
||||
test6_data: .word 75
|
||||
test7_data: .word 56
|
||||
test8_data: .word 83
|
||||
test9_data: .word 33
|
||||
test10_data: .word -65
|
||||
test11_data: .word -87
|
||||
test12_data: .word -55
|
||||
test13_data: .word 0xFFFF0004
|
||||
test14_data: .word 0xFFFF0005
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
MEMORY {
|
||||
onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
.crt_section :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*crt.o(.text)
|
||||
} > onChipRam
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue