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Add the linux config into the synthesis bench

This commit is contained in:
Charles Papon 2019-04-24 12:32:37 +02:00
parent a331f35724
commit 74e5cc49f9
1 changed files with 8 additions and 2 deletions
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10
src/main/scala/vexriscv/demo/SynthesisBench.scala
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@ -101,10 +101,16 @@ object VexRiscvSynthesisBench {
} }
val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) val linuxBalanced = new Rtl {
override def getName(): String = "VexRiscv linux balanced"
override def getRtlPath(): String = "VexRiscvLinuxBalanced.v"
SpinalConfig(inlineRom = true).generateVerilog(wrap(new VexRiscv(LinuxGen.configFull(false, true))).setDefinitionName(getRtlPath().split("\\.").head))
}
val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced)
// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) // val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache)
// val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full)
// val rtls = List(fullNoMmu) // val rtls = List(smallAndProductive)
val targets = XilinxStdTargets( val targets = XilinxStdTargets(
vivadoArtix7Path = "/media/miaou/HD/linux/Xilinx/Vivado/2018.3/bin" vivadoArtix7Path = "/media/miaou/HD/linux/Xilinx/Vivado/2018.3/bin"