Add the linux config into the synthesis bench
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@ -101,10 +101,16 @@ object VexRiscvSynthesisBench {
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}
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val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full)
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val linuxBalanced = new Rtl {
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override def getName(): String = "VexRiscv linux balanced"
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override def getRtlPath(): String = "VexRiscvLinuxBalanced.v"
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SpinalConfig(inlineRom = true).generateVerilog(wrap(new VexRiscv(LinuxGen.configFull(false, true))).setDefinitionName(getRtlPath().split("\\.").head))
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}
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val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced)
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// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache)
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// val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full)
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// val rtls = List(fullNoMmu)
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// val rtls = List(smallAndProductive)
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val targets = XilinxStdTargets(
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vivadoArtix7Path = "/media/miaou/HD/linux/Xilinx/Vivado/2018.3/bin"
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