d$ toBmb increase aggregation timer
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@ -400,7 +400,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
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def toBmb(syncPendingMax : Int = 32,
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def toBmb(syncPendingMax : Int = 32,
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timeoutCycles : Int = 16) : Bmb = new Area{
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timeoutCycles : Int = 32) : Bmb = new Area{
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setCompositeName(DataCacheMemBus.this, "Bridge", true)
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setCompositeName(DataCacheMemBus.this, "Bridge", true)
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val pipelinedMemoryBusConfig = p.getBmbParameter()
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val pipelinedMemoryBusConfig = p.getBmbParameter()
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val bus = Bmb(pipelinedMemoryBusConfig).setCompositeName(this,"toBmb", true)
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val bus = Bmb(pipelinedMemoryBusConfig).setCompositeName(this,"toBmb", true)
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