Static prediction is fully functionnal
This commit is contained in:
Dolu1990
parent
0919308a8f
commit
76ca852478
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@ -11,25 +11,71 @@ object STATIC extends BranchPrediction
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object DYNAMIC extends BranchPrediction
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object DYNAMIC_TARGET extends BranchPrediction
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object BranchCtrlEnum extends SpinalEnum(binarySequential){
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val INC,B,JAL,JALR = newElement()
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}
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object BRANCH_CTRL extends Stageable(BranchCtrlEnum())
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case class DecodePredictionCmd() extends Bundle {
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val hadBranch = Bool
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}
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case class DecodePredictionRsp(stage : Stage) extends Bundle {
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val wasWrong = Bool
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}
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case class DecodePredictionBus(stage : Stage) extends Bundle {
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val cmd = DecodePredictionCmd()
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val rsp = DecodePredictionRsp(stage)
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}
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case class FetchPredictionCmd() extends Bundle{
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val hadBranch = Bool
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val targetPc = UInt(32 bits)
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}
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case class FetchPredictionRsp(stage : Stage) extends Bundle{
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val wasRight = Bool
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val targetPc = UInt(32 bits)
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}
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case class FetchPredictionBus(stage : Stage) extends Bundle {
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val cmd = FetchPredictionCmd()
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val rsp = FetchPredictionRsp(stage)
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}
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trait PredictionInterface{
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def askFetchPrediction() : FetchPredictionBus
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def askDecodePrediction() : DecodePredictionBus
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}
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class BranchPlugin(earlyBranch : Boolean,
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catchAddressMisaligned : Boolean,
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prediction : BranchPrediction,
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historyRamSizeLog2 : Int = 10,
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historyWidth : Int = 2) extends Plugin[VexRiscv]{
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object BranchCtrlEnum extends SpinalEnum(binarySequential){
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val INC,B,JAL,JALR = newElement()
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}
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historyWidth : Int = 2) extends Plugin[VexRiscv] with PredictionInterface{
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lazy val branchStage = if(earlyBranch) pipeline.execute else pipeline.memory
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object BRANCH_CTRL extends Stageable(BranchCtrlEnum())
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object BRANCH_CALC extends Stageable(UInt(32 bits))
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object BRANCH_DO extends Stageable(Bool)
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object BRANCH_COND_RESULT extends Stageable(Bool)
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// object PREDICTION_HAD_BRANCHED extends Stageable(Bool)
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var jumpInterface : Flow[UInt] = null
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var predictionJumpInterface : Flow[UInt] = null
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var predictionExceptionPort : Flow[ExceptionCause] = null
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var branchExceptionPort : Flow[ExceptionCause] = null
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var decodePrediction : DecodePredictionBus = null
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override def askFetchPrediction() = ???
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override def askDecodePrediction() = {
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decodePrediction = DecodePredictionBus(branchStage)
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decodePrediction
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}
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override def setup(pipeline: VexRiscv): Unit = {
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import Riscv._
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import pipeline.config._
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@ -66,7 +112,7 @@ class BranchPlugin(earlyBranch : Boolean,
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))
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val pcManagerService = pipeline.service(classOf[JumpService])
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jumpInterface = pcManagerService.createJumpInterface(if(earlyBranch) pipeline.execute else pipeline.memory)
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jumpInterface = pcManagerService.createJumpInterface(branchStage)
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prediction match {
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case NONE =>
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@ -76,7 +122,7 @@ class BranchPlugin(earlyBranch : Boolean,
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if (catchAddressMisaligned) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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branchExceptionPort = exceptionService.newExceptionPort(if (earlyBranch) pipeline.execute else pipeline.memory)
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branchExceptionPort = exceptionService.newExceptionPort(branchStage)
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prediction match {
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case NONE =>
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// case STATIC | DYNAMIC => predictionExceptionPort = exceptionService.newExceptionPort(pipeline.decode)
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@ -85,9 +131,9 @@ class BranchPlugin(earlyBranch : Boolean,
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}
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}
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override def build(pipeline: VexRiscv): Unit = prediction match {
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case `NONE` => buildWithoutPrediction(pipeline)
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// case `STATIC` => buildWithPrediction(pipeline)
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override def build(pipeline: VexRiscv): Unit = (decodePrediction) match {
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case null => buildWithoutPrediction(pipeline)
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case _ => buildWithPrediction(pipeline)
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// case `DYNAMIC` => buildWithPrediction(pipeline)
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// case `DYNAMIC_TARGET` => buildDynamicTargetPrediction(pipeline)
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}
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@ -128,7 +174,6 @@ class BranchPlugin(earlyBranch : Boolean,
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}
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//Apply branchs (JAL,JALR, Bxx)
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val branchStage = if(earlyBranch) execute else memory
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branchStage plug new Area {
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import branchStage._
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jumpInterface.valid := arbitration.isFiring && input(BRANCH_DO)
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@ -147,21 +192,21 @@ class BranchPlugin(earlyBranch : Boolean,
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}
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// def buildWithPrediction(pipeline: VexRiscv): Unit = {
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def buildWithPrediction(pipeline: VexRiscv): Unit = {
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// case class BranchPredictorLine() extends Bundle{
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// val history = SInt(historyWidth bits)
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// }
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//
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// object PREDICTION_HAD_BRANCHED extends Stageable(Bool)
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object PREDICTION_HAD_BRANCHED extends Stageable(Bool)
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// object HISTORY_LINE extends Stageable(BranchPredictorLine())
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//
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// import pipeline._
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// import pipeline.config._
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//
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import pipeline._
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import pipeline.config._
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// val historyCache = if(prediction == DYNAMIC) Mem(BranchPredictorLine(), 1 << historyRamSizeLog2) setName("branchCache") else null
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// val historyCacheWrite = if(prediction == DYNAMIC) historyCache.writePort else null
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//
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// //Read historyCache
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//Read historyCache
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// if(prediction == DYNAMIC) fetch plug new Area{
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// val readAddress = prefetch.output(PC)(2, historyRamSizeLog2 bits)
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// fetch.insert(HISTORY_LINE) := historyCache.readSync(readAddress,!prefetch.arbitration.isStuckByOthers)
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@ -172,8 +217,8 @@ class BranchPlugin(earlyBranch : Boolean,
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//// fetch.insert(HISTORY_LINE) := writePortReg.data
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//// }
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// }
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//
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// //Branch JAL, predict Bxx and branch it
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//Branch JAL, predict Bxx and branch it
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// decode plug new Area{
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// import decode._
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// val imm = IMM(input(INSTRUCTION))
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@ -196,65 +241,71 @@ class BranchPlugin(earlyBranch : Boolean,
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// predictionExceptionPort.badAddr := predictionJumpInterface.payload
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// }
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// }
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//
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// //Do real branch calculation
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// execute plug new Area {
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// import execute._
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//
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// val less = input(SRC_LESS)
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// val eq = input(SRC1) === input(SRC2)
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//
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// insert(BRANCH_COND_RESULT) := input(BRANCH_CTRL).mux(
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// BranchCtrlEnum.INC -> False,
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// BranchCtrlEnum.JAL -> True,
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// BranchCtrlEnum.JALR -> True,
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// BranchCtrlEnum.B -> input(INSTRUCTION)(14 downto 12).mux(
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// B"000" -> eq ,
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// B"001" -> !eq ,
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// M"1-1" -> !less,
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// default -> less
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// )
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// )
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//
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// insert(BRANCH_DO) := input(PREDICTION_HAD_BRANCHED) =/= insert(BRANCH_COND_RESULT)
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//
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// //Calculation of the branch target / correction
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// val imm = IMM(input(INSTRUCTION))
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// val branch_src1,branch_src2 = UInt(32 bits)
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// switch(input(BRANCH_CTRL)){
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// is(BranchCtrlEnum.JALR){
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// branch_src1 := input(RS1).asUInt
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// branch_src2 := imm.i_sext.asUInt
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// }
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// default{
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// branch_src1 := input(PC)
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// branch_src2 := (input(PREDICTION_HAD_BRANCHED) ? B(4) | imm.b_sext).asUInt
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// }
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// }
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// val branchAdder = branch_src1 + branch_src2
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// insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ ((input(BRANCH_CTRL) === BranchCtrlEnum.JALR) ? False | branchAdder(0))
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// }
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//
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//
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// // branch JALR or JAL/Bxx prediction miss corrections
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// val branchStage = if(earlyBranch) execute else memory
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// branchStage plug new Area {
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// import branchStage._
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// jumpInterface.valid := input(BRANCH_DO) && arbitration.isFiring
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// jumpInterface.payload := input(BRANCH_CALC)
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//
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// when(jumpInterface.valid) {
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// stages(indexOf(branchStage) - 1).arbitration.flushAll := True
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// }
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//
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// if(catchAddressMisaligned) {
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// branchExceptionPort.valid := input(INSTRUCTION_READY) && arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
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// branchExceptionPort.code := 0
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// branchExceptionPort.badAddr := jumpInterface.payload
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// }
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// }
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//
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// //Update historyCache
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decode plug new Area {
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import decode._
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insert(PREDICTION_HAD_BRANCHED) := decodePrediction.cmd.hadBranch
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}
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//Do real branch calculation
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execute plug new Area {
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import execute._
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val less = input(SRC_LESS)
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val eq = input(SRC1) === input(SRC2)
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insert(BRANCH_COND_RESULT) := input(BRANCH_CTRL).mux(
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BranchCtrlEnum.INC -> False,
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BranchCtrlEnum.JAL -> True,
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BranchCtrlEnum.JALR -> True,
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BranchCtrlEnum.B -> input(INSTRUCTION)(14 downto 12).mux(
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B"000" -> eq ,
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B"001" -> !eq ,
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M"1-1" -> !less,
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default -> less
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)
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)
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insert(BRANCH_DO) := input(PREDICTION_HAD_BRANCHED) =/= insert(BRANCH_COND_RESULT)
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//Calculation of the branch target / correction
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val imm = IMM(input(INSTRUCTION))
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val branch_src1,branch_src2 = UInt(32 bits)
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switch(input(BRANCH_CTRL)){
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is(BranchCtrlEnum.JALR){
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branch_src1 := input(RS1).asUInt
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branch_src2 := imm.i_sext.asUInt
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}
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default{
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branch_src1 := input(PC)
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branch_src2 := (input(PREDICTION_HAD_BRANCHED) ? B(4) | imm.b_sext).asUInt
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}
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}
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val branchAdder = branch_src1 + branch_src2
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insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ ((input(BRANCH_CTRL) === BranchCtrlEnum.JALR) ? False | branchAdder(0))
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}
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// branch JALR or JAL/Bxx prediction miss corrections
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val branchStage = if(earlyBranch) execute else memory
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branchStage plug new Area {
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import branchStage._
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jumpInterface.valid := input(BRANCH_DO) && arbitration.isFiring
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jumpInterface.payload := input(BRANCH_CALC)
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when(jumpInterface.valid) {
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stages(indexOf(branchStage) - 1).arbitration.flushAll := True
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}
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if(catchAddressMisaligned) {
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branchExceptionPort.valid := input(INSTRUCTION_READY) && arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
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branchExceptionPort.code := 0
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branchExceptionPort.badAddr := jumpInterface.payload
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}
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}
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//Update historyCache
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decodePrediction.rsp.wasWrong := jumpInterface.valid
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// if(prediction == DYNAMIC) branchStage plug new Area {
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// import branchStage._
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// val newHistory = input(HISTORY_LINE).history.resize(historyWidth + 1) + Mux(input(BRANCH_COND_RESULT),S(-1),S(1))
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@ -264,7 +315,7 @@ class BranchPlugin(earlyBranch : Boolean,
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// historyCacheWrite.address := input(PC)(2, historyRamSizeLog2 bits)
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// historyCacheWrite.data.history := newHistory.resized
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// }
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// }
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}
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@ -5,6 +5,7 @@ import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba4.axi._
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import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
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import vexriscv.Riscv.IMM
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import scala.collection.mutable.ArrayBuffer
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@ -109,12 +110,14 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
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var prefetchExceptionPort : Flow[ExceptionCause] = null
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def resetVector = BigInt(0x80000000l)
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def keepPcPlus4 = false
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def decodePcGen = true
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def compressedGen = true
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def decodePcGen = false
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def compressedGen = false
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def cmdToRspStageCount = 1
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def rspStageGen = false
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def injectorReadyCutGen = true
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def relaxedPcCalculation = true
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def injectorReadyCutGen = false
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def relaxedPcCalculation = false
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def prediction : BranchPrediction = STATIC
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var decodePrediction : DecodePredictionBus = null
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assert(cmdToRspStageCount >= 1)
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assert(!(compressedGen && !decodePcGen))
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lazy val fetcherHalt = False
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@ -122,6 +125,8 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
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lazy val decodeNextPc = UInt(32 bits)
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def nextPc() = (decodeNextPcValid, decodeNextPc)
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var predictionJumpInterface : Flow[UInt] = null
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override def haltIt(): Unit = fetcherHalt := True
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case class JumpInfo(interface : Flow[UInt], stage: Stage, priority : Int)
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@ -142,6 +147,14 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
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}
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pipeline(RVC_GEN) = compressedGen
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prediction match {
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case NONE =>
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case STATIC | DYNAMIC => {
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predictionJumpInterface = createJumpInterface(pipeline.decode)
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decodePrediction = pipeline.service(classOf[PredictionInterface]).askDecodePrediction()
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}
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}
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}
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override def build(pipeline: VexRiscv): Unit = {
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@ -365,6 +378,29 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
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decodeExceptionPort.code := 1
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decodeExceptionPort.badAddr := decode.input(PC)
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}
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prediction match {
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case `NONE` =>
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case `STATIC` => {
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val imm = IMM(decode.input(INSTRUCTION))
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val conditionalBranchPrediction = (prediction match {
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case `STATIC` => imm.b_sext.msb
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//case `DYNAMIC` => input(HISTORY_LINE).history.msb
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})
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decodePrediction.cmd.hadBranch := decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL || (decode.input(BRANCH_CTRL) === BranchCtrlEnum.B && conditionalBranchPrediction)
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predictionJumpInterface.valid := decodePrediction.cmd.hadBranch && decode.arbitration.isFiring //TODO OH Doublon de priorité
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predictionJumpInterface.payload := decode.input(PC) + ((decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL) ? imm.j_sext | imm.b_sext).asUInt
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// if(catchAddressMisaligned) {
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// predictionExceptionPort.valid := input(INSTRUCTION_READY) && input(PREDICTION_HAD_BRANCHED) && arbitration.isValid && predictionJumpInterface.payload(1 downto 0) =/= 0
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// predictionExceptionPort.code := 0
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// predictionExceptionPort.badAddr := predictionJumpInterface.payload
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// }
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}
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}
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}
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}
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}
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