Add many cpu configs on regressions tests (some config are broken)
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Dolu1990
parent
8729530a8d
commit
7768f065e4
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@ -3,8 +3,18 @@ package vexriscv
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import vexriscv.plugin._
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import spinal.core._
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case class VexRiscvConfig(plugins : Seq[Plugin[VexRiscv]]){
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import scala.collection.mutable.ArrayBuffer
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object VexRiscvConfig{
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def apply(plugins : Seq[Plugin[VexRiscv]]) : VexRiscvConfig = {
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val config = VexRiscvConfig()
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config.plugins ++= plugins
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config
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}
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}
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case class VexRiscvConfig(){
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val plugins = ArrayBuffer[Plugin[VexRiscv]]()
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//Default Stageables
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object IS_RVC extends Stageable(Bool)
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@ -49,8 +49,7 @@ trait PredictionInterface{
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}
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class BranchPlugin(earlyBranch : Boolean,
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catchAddressMisaligned : Boolean,
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historyWidth : Int = 2) extends Plugin[VexRiscv] with PredictionInterface{
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catchAddressMisaligned : Boolean) extends Plugin[VexRiscv] with PredictionInterface{
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lazy val branchStage = if(earlyBranch) pipeline.execute else pipeline.memory
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@ -0,0 +1,306 @@
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package vexriscv
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import java.io.File
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import org.scalatest.FunSuite
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import spinal.core.SpinalVerilog
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import vexriscv.demo._
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import vexriscv.plugin._
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import scala.collection.mutable.ArrayBuffer
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import scala.sys.process._
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abstract class ConfigDimension[T](val name: String) {
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def positions: Seq[T]
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def default : Seq[T] = List(positions(0))
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}
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abstract class VexRiscvDimension(name: String) extends ConfigDimension[VexRiscvPosition](name)
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class ShiftDimension extends VexRiscvDimension("Shift") {
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override val positions = List(
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new VexRiscvPosition("FullLate") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new FullBarrielShifterPlugin(earlyInjection = false)
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},
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new VexRiscvPosition("FullEarly") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new FullBarrielShifterPlugin(earlyInjection = true)
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},
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new VexRiscvPosition("Light") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new LightShifterPlugin
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}
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)
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}
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class BranchDimension extends VexRiscvDimension("Branch") {
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override val positions = List(
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new VexRiscvPosition("Late") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false
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)
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},
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new VexRiscvPosition("Early") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new BranchPlugin(
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earlyBranch = true,
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catchAddressMisaligned = false
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)
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}
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)
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}
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class MulDivDimension extends VexRiscvDimension("MulDiv") {
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override val positions = List(
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new VexRiscvPosition("NoMulDiv") {
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override def applyOn(config: VexRiscvConfig): Unit = {}
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override def testParam = "MUL=no DIV=no"
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},
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new VexRiscvPosition("MulDiv") {
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override def testParam = "MUL=yes DIV=yes"
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override def applyOn(config: VexRiscvConfig): Unit = {
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config.plugins += new MulPlugin
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config.plugins += new MulDivIterativePlugin(
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genMul = false,
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genDiv = true,
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mulUnroolFactor = 32,
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divUnroolFactor = 1
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)
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}
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}
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)
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}
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class RegFileDimension extends VexRiscvDimension("RegFile") {
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override val positions = List(
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new VexRiscvPosition("Async") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new RegFilePlugin(
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regFileReadyKind = plugin.ASYNC
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)
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},
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new VexRiscvPosition("Sync") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new RegFilePlugin(
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regFileReadyKind = plugin.SYNC
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)
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}
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)
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}
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class HazardDimension extends VexRiscvDimension("Hazard") {
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override val positions = List(
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new VexRiscvPosition("Interlock") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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)
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},
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new VexRiscvPosition("BypassAll") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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)
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},
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new VexRiscvPosition("BypassExecute") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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)
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},
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new VexRiscvPosition("BypassMemory") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = true,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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)
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},
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new VexRiscvPosition("BypassWriteBack") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = true,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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)
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},
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new VexRiscvPosition("BypassWriteBackBuffer") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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)
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}
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)
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}
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class SrcDimension extends VexRiscvDimension("Src") {
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override val positions = List(
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new VexRiscvPosition("Early") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = false
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)
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},
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new VexRiscvPosition("Late") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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)
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},
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new VexRiscvPosition("AddSub") {
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new SrcPlugin(
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separatedAddSub = true,
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executeInsertion = false
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)
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}
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)
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}
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class IBusDimension extends VexRiscvDimension("IBus") {
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override val positions = (for(prediction <- List(NONE, STATIC, DYNAMIC, DYNAMIC_TARGET);
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latency <- List(1,3);
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compressed <- List(false, true);
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injectorStage <- List(false, true);
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relaxedPcCalculation <- List(false, true);
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if latency > 1 || injectorStage) yield new VexRiscvPosition("Simple" + latency + (if(relaxedPcCalculation) "Relax" else "") + (if(injectorStage) "InjStage" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")) {
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override def testParam = "IBUS=SIMPLE" + (if(compressed) " COMPRESSED=yes" else "")
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusSimplePlugin(
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resetVector = 0x80000000l,
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relaxedPcCalculation = relaxedPcCalculation,
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prediction = prediction,
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catchAccessFault = false,
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compressedGen = compressed,
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busLatencyMin = latency,
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injectorStage = injectorStage
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)
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}) :+ new VexRiscvPosition("FullRelaxed"){
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override def testParam = "IBUS=SIMPLE"
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusSimplePlugin(
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resetVector = 0x80000000l,
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relaxedPcCalculation = true,
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relaxedBusCmdValid = true,
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prediction = STATIC,
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catchAccessFault = false,
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compressedGen = true,
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busLatencyMin = 3,
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injectorStage = true
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)
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}
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}
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abstract class ConfigPosition[T](val name: String) {
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def applyOn(config: T): Unit
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var dimension : ConfigDimension[_] = null
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}
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abstract class VexRiscvPosition(name: String) extends ConfigPosition[VexRiscvConfig](name){
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def testParam : String = ""
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}
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class TestIndividualFeatures extends FunSuite {
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def doCmd(cmd: String): String = {
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val stdOut = new StringBuilder()
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class Logger extends ProcessLogger {
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override def err(s: => String): Unit = {
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if (!s.startsWith("ar: creating ")) println(s)
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}
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override def out(s: => String): Unit = {
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println(s)
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stdOut ++= s
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}
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override def buffer[T](f: => T) = f
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}
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Process(cmd, new File("src/test/cpp/regression")).!(new Logger)
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stdOut.toString()
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}
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val dimensions = List(
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new MulDivDimension,
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new ShiftDimension,
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new BranchDimension,
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new HazardDimension,
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new RegFileDimension,
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new SrcDimension,
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new IBusDimension
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)
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def genDefaultsPositions(dims : Seq[VexRiscvDimension], stack : List[VexRiscvPosition] = Nil) : Seq[List[VexRiscvPosition]] = dims match {
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case head :: tail => head.default.flatMap(p => genDefaultsPositions(tail, p :: stack))
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case Nil => List(stack)
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}
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dimensions.foreach(d => d.positions.foreach(_.dimension = d))
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for (dimension <- dimensions) {
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for (position <- dimension.positions) {
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for(defaults <- genDefaultsPositions(dimensions.filter(_ != dimension))){
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def gen = {
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val config = VexRiscvConfig(
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plugins = List(
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new IntAluPlugin,
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new YamlPlugin("cpu0.yaml")
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)
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)
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position.applyOn(config)
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for (dimensionOthers <- defaults) dimensionOthers.applyOn(config)
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SpinalVerilog(new VexRiscv(config))
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}
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val name = dimension.name + "_ " + position.name + "_" + defaults.map(d => d.dimension.name + "_" + d.name).mkString("_")
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test(name + "_gen") {
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gen
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}
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test(name + "_test") {
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val testCmd = "make clean run REDO=10 DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no " + (position :: defaults).map(_.testParam).mkString(" ")
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val str = doCmd(testCmd)
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assert(!str.contains("FAIL"))
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val intFind = "(\\d+\\.?)+".r
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val dmips = intFind.findFirstIn("DMIPS per Mhz\\: (\\d+.?)+".r.findAllIn(str).toList.last).get.toDouble
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}
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}
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}
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}
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}
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