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Add AES-instruction support

This commit is contained in:
Dolu1990 2020-12-21 11:50:54 +01:00
parent c59499ec03
commit 780ad01ac0
1 changed files with 9 additions and 5 deletions
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14
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
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@ -6,7 +6,7 @@ import spinal.lib.bus.misc.{AddressMapping, DefaultMapping, SizeMapping}
import spinal.lib.bus.wishbone.{WishboneConfig, WishboneToBmbGenerator} import spinal.lib.bus.wishbone.{WishboneConfig, WishboneToBmbGenerator}
import spinal.lib.sim.SparseMemory import spinal.lib.sim.SparseMemory
import vexriscv.demo.smp.VexRiscvSmpClusterGen.vexRiscvConfig import vexriscv.demo.smp.VexRiscvSmpClusterGen.vexRiscvConfig
import vexriscv.plugin.DBusCachedPlugin import vexriscv.plugin.{AesPlugin, DBusCachedPlugin}
case class VexRiscvLitexSmpClusterParameter( cluster : VexRiscvSmpClusterParameter, case class VexRiscvLitexSmpClusterParameter( cluster : VexRiscvSmpClusterParameter,
@ -66,6 +66,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
var dCacheWays = 2 var dCacheWays = 2
var liteDramWidth = 128 var liteDramWidth = 128
var coherentDma = false var coherentDma = false
var aesInstruction = false
var netlistDirectory = "." var netlistDirectory = "."
var netlistName = "VexRiscvLitexSmpCluster" var netlistName = "VexRiscvLitexSmpCluster"
assert(new scopt.OptionParser[Unit]("VexRiscvLitexSmpClusterCmdGen") { assert(new scopt.OptionParser[Unit]("VexRiscvLitexSmpClusterCmdGen") {
@ -81,13 +82,14 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
opt[String]("litedram-width") action { (v, c) => liteDramWidth = v.toInt } opt[String]("litedram-width") action { (v, c) => liteDramWidth = v.toInt }
opt[String]("netlist-directory") action { (v, c) => netlistDirectory = v } opt[String]("netlist-directory") action { (v, c) => netlistDirectory = v }
opt[String]("netlist-name") action { (v, c) => netlistName = v } opt[String]("netlist-name") action { (v, c) => netlistName = v }
opt[String]("aes-instruction") action { (v, c) => aesInstruction = v.toBoolean }
}.parse(args)) }.parse(args))
val coherency = coherentDma || cpuCount > 1 val coherency = coherentDma || cpuCount > 1
def parameter = VexRiscvLitexSmpClusterParameter( def parameter = VexRiscvLitexSmpClusterParameter(
cluster = VexRiscvSmpClusterParameter( cluster = VexRiscvSmpClusterParameter(
cpuConfigs = List.tabulate(cpuCount) { hartId => cpuConfigs = List.tabulate(cpuCount) { hartId => {
vexRiscvConfig( val c = vexRiscvConfig(
hartId = hartId, hartId = hartId,
ioRange = address => address.msb, ioRange = address => address.msb,
resetVector = 0, resetVector = 0,
@ -99,7 +101,9 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
dCacheWays = dCacheWays, dCacheWays = dCacheWays,
coherency = coherency coherency = coherency
) )
}, if(aesInstruction) c.add(new AesPlugin)
c
}},
withExclusiveAndInvalidation = coherency withExclusiveAndInvalidation = coherency
), ),
liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = liteDramWidth), liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = liteDramWidth),
@ -114,7 +118,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
toplevel toplevel
} }
val genConfig = SpinalConfig(targetDirectory = netlistDirectory).addStandardMemBlackboxing(blackboxByteEnables) val genConfig = SpinalConfig(targetDirectory = netlistDirectory, inlineRom = true).addStandardMemBlackboxing(blackboxByteEnables)
genConfig.generateVerilog(dutGen.setDefinitionName(netlistName)) genConfig.generateVerilog(dutGen.setDefinitionName(netlistName))
} }