Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity

update gcc path

Browse source
This commit is contained in:
Charles Papon 2017-08-14 12:16:40 +02:00
parent 8fbd777794
commit 7811d90f99
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
README.md
View file

@ -298,7 +298,7 @@ There is some scripts to generate the SoC and call the icestorm toolchain there
In fact, you can find some prebuild GCC : <br>
- https://www.sifive.com/products/tools/ => SiFive GNU Embedded Toolchain
The VexRiscvSocSoftware makefiles are expecting to find this prebuild version in /opt/rv/__contentOfThisPreBuild__
The VexRiscvSocSoftware makefiles are expecting to find this prebuild version in /opt/riscv/__contentOfThisPreBuild__
But if you want to compile from sources in /opt/ the rv32i and rv32im gcc, do the following (will take hours):