Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'dev' into rework_fetch 

# Conflicts:
#	src/test/scala/vexriscv/TestIndividualFeatures.scala
This commit is contained in:
Dolu1990 2020-03-01 22:58:25 +01:00
parent 25d880f6c7 ea5464ea26
commit 78d4660282
4 changed files with 226 additions and 108 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
README.md
View File

@ -185,24 +185,47 @@ NOTES:
[![Build Status](https://travis-ci.org/SpinalHDL/VexRiscv.svg?branch=master)](https://travis-ci.org/SpinalHDL/VexRiscv) [![Build Status](https://travis-ci.org/SpinalHDL/VexRiscv.svg?branch=master)](https://travis-ci.org/SpinalHDL/VexRiscv)
To run tests (need the verilator simulator), go in the src/test/cpp/regression folder and run : To run tests (need java, scala, verilator), just do :
```sh ```sh
# To test the GenFull CPU export VEXRISCV_REGRESSION_SEED=42
# (Don't worry about the CSR test not passing, basicaly the GenFull isn't the truly full version of the CPU, some CSR features are disable in it) export VEXRISCV_REGRESSION_TEST_ID=
make clean run sbt "testOnly vexriscv.TestIndividualFeatures"
# To test the GenSmallest CPU
make clean run IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no
``` ```
The self-test includes: This will generate random VexRiscv configuration and test them with:
- ISA tests from https://github.com/riscv/riscv-tests/tree/master/isa - ISA tests from https://github.com/riscv/riscv-tests/tree/master/isa and https://github.com/riscv/riscv-compliance
- Dhrystone benchmark - Dhrystone benchmark
- 24 FreeRTOS tests - Coremark benchmark
- Zephyr os
- Buildroot/Linux os
- Some handwritten tests to check the CSR, debug module and MMU plugins - Some handwritten tests to check the CSR, debug module and MMU plugins
You can enable FreeRTOS tests by adding `FREERTOS=yes` to the command line, but it will take time to run. Also, it uses THREAD_COUNT host CPU threads to run multiple regression in parallel. You can rerun some specific test by setting VEXRISCV_REGRESSION_TEST_ID by their id. For instance, if you want to rerun :
- test_id_5_test_IBus_CachedS1024W1BPL32Relaxvexriscv.plugin.DYNAMIC_DBus_CachedS8192W2BPL16_MulDiv_MulDivFpga_Shift_FullLate_Branch_Late_Hazard_BypassAll_RegFile_SyncDR_Src__Csr_AllNoException_Decoder__Debug_None_DBus_NoMmu
- test_id_9_test_IBus_Simple1S2InjStagevexriscv.plugin.STATIC_DBus_SimpleLate_MulDiv_MulDivFpgaSimple_Shift_FullEarly_Branch_Late_Hazard_Interlock_RegFile_AsyncER_Src_AddSubExecute_Csr_None_Decoder__Debug_None_DBus_NoMmu
then :
```
export VEXRISCV_REGRESSION_TEST_ID=5,9
```
Also there is a few environnement variable that you can use to modulate the random generation :
| Parameters | range | description |
| ------------------------------------------- | ------------------ | ----------- |
| VEXRISCV_REGRESSION_SEED | Int | Seed used to generate the random configurations |
| VEXRISCV_REGRESSION_TEST_ID | \[Int\[,\Int\]\*\] | Random configuration that should be keeped and tested |
| VEXRISCV_REGRESSION_CONFIG_COUNT | Int | Number of random configurations |
| VEXRISCV_REGRESSION_CONFIG_RVC_RATE | 0.0-1.0 | Chance to generate a RVC config |
| VEXRISCV_REGRESSION_CONFIG_LINUX_RATE | 0.0-1.0 | Chance to generate a linux ready config |
| VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE | 0.0-1.0 | Chance to generate a machine mode OS ready config |
| VEXRISCV_REGRESSION_LINUX_REGRESSION | yes/no | Enable the linux test |
| VEXRISCV_REGRESSION_COREMARK | yes/no | Enable the Coremark test |
| VEXRISCV_REGRESSION_ZEPHYR_COUNT | Int | Number of zephyr tests to run on capable configs |
| VEXRISCV_REGRESSION_CONFIG_DEMW_RATE | 0.0-1.0 | Chance to generate a config with writeback stage |
| VEXRISCV_REGRESSION_CONFIG_DEM_RATE | 0.0-1.0 | Chance to generate a config with memory stage |
## Interactive debug of the simulated CPU via GDB OpenOCD and Verilator ## Interactive debug of the simulated CPU via GDB OpenOCD and Verilator
It's as described to run tests, but you just have to add `DEBUG_PLUGIN_EXTERNAL=yes` in the make arguments. It's as described to run tests, but you just have to add `DEBUG_PLUGIN_EXTERNAL=yes` in the make arguments.

58
src/test/cpp/regression/main.cpp
View File

@ -2805,7 +2805,7 @@ public:
uint32_t regFileWriteRefIndex = 0; uint32_t regFileWriteRefIndex = 0;
TestA() : WorkspaceRegression("testA") { TestA() : WorkspaceRegression("testA") {
loadHex("../../resources/hex/testA.hex"); loadHex(string(REGRESSION_PATH) + "../../resources/hex/testA.hex");
} }
virtual void checks(){ virtual void checks(){
@ -2831,7 +2831,7 @@ public:
TestX28(string name, uint32_t *ref, uint32_t refSize) : WorkspaceRegression(name) { TestX28(string name, uint32_t *ref, uint32_t refSize) : WorkspaceRegression(name) {
this->ref = ref; this->ref = ref;
this->refSize = refSize; this->refSize = refSize;
loadHex("../../resources/hex/" + name + ".hex"); loadHex(string(REGRESSION_PATH) + "../../resources/hex/" + name + ".hex");
} }
virtual void checks(){ virtual void checks(){
@ -2851,7 +2851,7 @@ public:
class RiscvTest : public WorkspaceRegression{ class RiscvTest : public WorkspaceRegression{
public: public:
RiscvTest(string name) : WorkspaceRegression(name) { RiscvTest(string name) : WorkspaceRegression(name) {
loadHex("../../resources/hex/" + name + ".hex"); loadHex(string(REGRESSION_PATH) + "../../resources/hex/" + name + ".hex");
bootAt(0x800000bcu); bootAt(0x800000bcu);
} }
@ -2899,7 +2899,7 @@ public:
setIStall(iStall); setIStall(iStall);
setDStall(dStall); setDStall(dStall);
withRiscvRef(); withRiscvRef();
loadHex("../../resources/hex/" + hexName + ".hex"); loadHex(string(REGRESSION_PATH) + "../../resources/hex/" + hexName + ".hex");
this->hexName = hexName; this->hexName = hexName;
} }
@ -2942,7 +2942,7 @@ public:
int out32Counter = 0; int out32Counter = 0;
Compliance(string name) : WorkspaceRegression(name) { Compliance(string name) : WorkspaceRegression(name) {
withRiscvRef(); withRiscvRef();
loadHex("../../resources/hex/" + name + ".elf.hex"); loadHex(string(REGRESSION_PATH) + "../../resources/hex/" + name + ".elf.hex");
out32.open (name + ".out32"); out32.open (name + ".out32");
this->name = name; this->name = name;
} }
@ -2963,7 +2963,7 @@ public:
virtual void pass(){ virtual void pass(){
FILE *refFile = fopen((string("../../resources/ref/") + name + ".reference_output").c_str(), "r"); FILE *refFile = fopen((string(REGRESSION_PATH) + string("../../resources/ref/") + name + ".reference_output").c_str(), "r");
fseek(refFile, 0, SEEK_END); fseek(refFile, 0, SEEK_END);
uint32_t refSize = ftell(refFile); uint32_t refSize = ftell(refFile);
fseek(refFile, 0, SEEK_SET); fseek(refFile, 0, SEEK_SET);
@ -3152,7 +3152,7 @@ public:
DebugPluginTest() : WorkspaceRegression("DebugPluginTest") { DebugPluginTest() : WorkspaceRegression("DebugPluginTest") {
loadHex("../../resources/hex/debugPlugin.hex"); loadHex(string(REGRESSION_PATH) + "../../resources/hex/debugPlugin.hex");
pthread_create(&clientThreadId, NULL, &clientThreadWrapper, this); pthread_create(&clientThreadId, NULL, &clientThreadWrapper, this);
} }
@ -3837,17 +3837,17 @@ int main(int argc, char **argv, char **env) {
// #endif // #endif
#ifdef IBUS_CACHED #ifdef IBUS_CACHED
redo(REDO,WorkspaceRegression("icache").withRiscvRef()->loadHex("../raw/icache/build/icache.hex")->bootAt(0x80000000u)->run(50e3);); redo(REDO,WorkspaceRegression("icache").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../raw/icache/build/icache.hex")->bootAt(0x80000000u)->run(50e3););
#endif #endif
#ifdef DBUS_CACHED #ifdef DBUS_CACHED
redo(REDO,WorkspaceRegression("dcache").loadHex("../raw/dcache/build/dcache.hex")->bootAt(0x80000000u)->run(2500e3);); redo(REDO,WorkspaceRegression("dcache").loadHex(string(REGRESSION_PATH) + "../raw/dcache/build/dcache.hex")->bootAt(0x80000000u)->run(2500e3););
#endif #endif
#ifdef MMU #ifdef MMU
redo(REDO,WorkspaceRegression("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3);); redo(REDO,WorkspaceRegression("mmu").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
#endif #endif
#ifdef SUPERVISOR #ifdef SUPERVISOR
redo(REDO,WorkspaceRegression("deleg").withRiscvRef()->loadHex("../raw/deleg/build/deleg.hex")->bootAt(0x80000000u)->run(50e3);); redo(REDO,WorkspaceRegression("deleg").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../raw/deleg/build/deleg.hex")->bootAt(0x80000000u)->run(50e3););
#endif #endif
#ifdef DEBUG_PLUGIN #ifdef DEBUG_PLUGIN
@ -3858,20 +3858,20 @@ int main(int argc, char **argv, char **env) {
#endif #endif
#ifdef CUSTOM_SIMD_ADD #ifdef CUSTOM_SIMD_ADD
redo(REDO,WorkspaceRegression("custom_simd_add").loadHex("../custom/simd_add/build/custom_simd_add.hex")->bootAt(0x00000000u)->run(50e3);); redo(REDO,WorkspaceRegression("custom_simd_add").loadHex(string(REGRESSION_PATH) + "../custom/simd_add/build/custom_simd_add.hex")->bootAt(0x00000000u)->run(50e3););
#endif #endif
#ifdef CUSTOM_CSR #ifdef CUSTOM_CSR
redo(REDO,WorkspaceRegression("custom_csr").loadHex("../custom/custom_csr/build/custom_csr.hex")->bootAt(0x00000000u)->run(50e3);); redo(REDO,WorkspaceRegression("custom_csr").loadHex(string(REGRESSION_PATH) + "../custom/custom_csr/build/custom_csr.hex")->bootAt(0x00000000u)->run(50e3););
#endif #endif
#ifdef LRSC #ifdef LRSC
redo(REDO,WorkspaceRegression("lrsc").withRiscvRef()->loadHex("../raw/lrsc/build/lrsc.hex")->bootAt(0x00000000u)->run(10e3);); redo(REDO,WorkspaceRegression("lrsc").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../raw/lrsc/build/lrsc.hex")->bootAt(0x00000000u)->run(10e3););
#endif #endif
#ifdef AMO #ifdef AMO
redo(REDO,WorkspaceRegression("amo").withRiscvRef()->loadHex("../raw/amo/build/amo.hex")->bootAt(0x00000000u)->run(10e3);); redo(REDO,WorkspaceRegression("amo").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../raw/amo/build/amo.hex")->bootAt(0x00000000u)->run(10e3););
#endif #endif
#ifdef DHRYSTONE #ifdef DHRYSTONE
@ -3910,7 +3910,7 @@ int main(int argc, char **argv, char **env) {
if(withStall == -1) break; if(withStall == -1) break;
#endif #endif
WorkspaceRegression("coremark_" + rv + (withStall > 0 ? "_stall" : "_nostall")).withRiscvRef() WorkspaceRegression("coremark_" + rv + (withStall > 0 ? "_stall" : "_nostall")).withRiscvRef()
->loadBin("../../resources/bin/coremark_" + rv + ".bin", 0x80000000) ->loadBin(string(REGRESSION_PATH) + "../../resources/bin/coremark_" + rv + ".bin", 0x80000000)
->bootAt(0x80000000) ->bootAt(0x80000000)
->setIStall(withStall > 0) ->setIStall(withStall > 0)
->setDStall(withStall > 0) ->setDStall(withStall > 0)
@ -3930,17 +3930,17 @@ int main(int argc, char **argv, char **env) {
/*for(int redo = 0;redo < 4;redo++)*/{ /*for(int redo = 0;redo < 4;redo++)*/{
for(const string &name : freeRtosTests){ for(const string &name : freeRtosTests){
tasks.push_back([=]() { WorkspaceRegression(name + "_rv32i_O0").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32i_O0.hex")->bootAt(0x80000000u)->run(4e6*15);}); tasks.push_back([=]() { WorkspaceRegression(name + "_rv32i_O0").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/freertos/" + name + "_rv32i_O0.hex")->bootAt(0x80000000u)->run(4e6*15);});
tasks.push_back([=]() { WorkspaceRegression(name + "_rv32i_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32i_O3.hex")->bootAt(0x80000000u)->run(4e6*15);}); tasks.push_back([=]() { WorkspaceRegression(name + "_rv32i_O3").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/freertos/" + name + "_rv32i_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
#ifdef COMPRESSED #ifdef COMPRESSED
// tasks.push_back([=]() { WorkspaceRegression(name + "_rv32ic_O0").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32ic_O0.hex")->bootAt(0x80000000u)->run(5e6*15);}); // tasks.push_back([=]() { WorkspaceRegression(name + "_rv32ic_O0").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/freertos/" + name + "_rv32ic_O0.hex")->bootAt(0x80000000u)->run(5e6*15);});
tasks.push_back([=]() { WorkspaceRegression(name + "_rv32ic_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32ic_O3.hex")->bootAt(0x80000000u)->run(4e6*15);}); tasks.push_back([=]() { WorkspaceRegression(name + "_rv32ic_O3").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/freertos/" + name + "_rv32ic_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
#endif #endif
#if defined(MUL) && defined(DIV) #if defined(MUL) && defined(DIV)
// #ifdef COMPRESSED // #ifdef COMPRESSED
// tasks.push_back([=]() { WorkspaceRegression(name + "_rv32imac_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32imac_O3.hex")->bootAt(0x80000000u)->run(4e6*15);}); // tasks.push_back([=]() { WorkspaceRegression(name + "_rv32imac_O3").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/freertos/" + name + "_rv32imac_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
// #else // #else
tasks.push_back([=]() { WorkspaceRegression(name + "_rv32im_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32im_O3.hex")->bootAt(0x80000000u)->run(4e6*15);}); tasks.push_back([=]() { WorkspaceRegression(name + "_rv32im_O3").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/freertos/" + name + "_rv32im_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
// #endif // #endif
#endif #endif
} }
@ -3967,12 +3967,12 @@ int main(int argc, char **argv, char **env) {
/*for(int redo = 0;redo < 4;redo++)*/{ /*for(int redo = 0;redo < 4;redo++)*/{
for(const string &name : zephyrTests){ for(const string &name : zephyrTests){
#ifdef COMPRESSED #ifdef COMPRESSED
tasks.push_back([=]() { ZephyrRegression(name + "_rv32ic").withRiscvRef()->loadHex("../../resources/VexRiscvRegressionData/sim/zephyr/" + name + "_rv32ic.hex")->bootAt(0x80000000u)->run(180e6);}); tasks.push_back([=]() { ZephyrRegression(name + "_rv32ic").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/VexRiscvRegressionData/sim/zephyr/" + name + "_rv32ic.hex")->bootAt(0x80000000u)->run(180e6);});
#else #else
tasks.push_back([=]() { ZephyrRegression(name + "_rv32i").withRiscvRef()->loadHex("../../resources/VexRiscvRegressionData/sim/zephyr/" + name + "_rv32i.hex")->bootAt(0x80000000u)->run(180e6);}); tasks.push_back([=]() { ZephyrRegression(name + "_rv32i").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/VexRiscvRegressionData/sim/zephyr/" + name + "_rv32i.hex")->bootAt(0x80000000u)->run(180e6);});
#endif #endif
#if defined(MUL) && defined(DIV) #if defined(MUL) && defined(DIV)
tasks.push_back([=]() { ZephyrRegression(name + "_rv32im").withRiscvRef()->loadHex("../../resources/VexRiscvRegressionData/sim/zephyr/" + name + "_rv32im.hex")->bootAt(0x80000000u)->run(180e6);}); tasks.push_back([=]() { ZephyrRegression(name + "_rv32im").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/VexRiscvRegressionData/sim/zephyr/" + name + "_rv32im.hex")->bootAt(0x80000000u)->run(180e6);});
#endif #endif
} }
} }
@ -3993,10 +3993,10 @@ int main(int argc, char **argv, char **env) {
LinuxRegression soc("linux"); LinuxRegression soc("linux");
#ifndef DEBUG_PLUGIN_EXTERNAL #ifndef DEBUG_PLUGIN_EXTERNAL
soc.withRiscvRef(); soc.withRiscvRef();
soc.loadBin(EMULATOR, 0x80000000); soc.loadBin(string(REGRESSION_PATH) + EMULATOR, 0x80000000);
soc.loadBin(VMLINUX, 0xC0000000); soc.loadBin(string(REGRESSION_PATH) + VMLINUX, 0xC0000000);
soc.loadBin(DTB, 0xC3000000); soc.loadBin(string(REGRESSION_PATH) + DTB, 0xC3000000);
soc.loadBin(RAMDISK, 0xC2000000); soc.loadBin(string(REGRESSION_PATH) + RAMDISK, 0xC2000000);
#endif #endif
//soc.setIStall(true); //soc.setIStall(true);
//soc.setDStall(true); //soc.setDStall(true);

15
src/test/cpp/regression/makefile
View File

@ -1,5 +1,6 @@
DEBUG?=no DEBUG?=no
REGRESSION_PATH?=./
VEXRISCV_FILE?=../../../../VexRiscv.v
IBUS?=CACHED IBUS?=CACHED
IBUS_TC?=no IBUS_TC?=no
DBUS?=CACHED DBUS?=CACHED
@ -38,6 +39,7 @@ STOP_ON_ERROR?=no
COREMARK=no COREMARK=no
WITH_USER_IO?=no WITH_USER_IO?=no
ADDCFLAGS += -CFLAGS -DREGRESSION_PATH='\"$(REGRESSION_PATH)/\"'
ADDCFLAGS += -CFLAGS -DIBUS_${IBUS} ADDCFLAGS += -CFLAGS -DIBUS_${IBUS}
ADDCFLAGS += -CFLAGS -DDBUS_${DBUS} ADDCFLAGS += -CFLAGS -DDBUS_${DBUS}
ADDCFLAGS += -CFLAGS -DREDO=${REDO} ADDCFLAGS += -CFLAGS -DREDO=${REDO}
@ -107,11 +109,11 @@ endif
ifneq ($(shell grep timerInterrupt ../../../../VexRiscv.v -w),) ifneq ($(shell grep timerInterrupt ${VEXRISCV_FILE} -w),)
ADDCFLAGS += -CFLAGS -DTIMER_INTERRUPT ADDCFLAGS += -CFLAGS -DTIMER_INTERRUPT
endif endif
ifneq ($(shell grep externalInterrupt ../../../../VexRiscv.v -w),) ifneq ($(shell grep externalInterrupt ${VEXRISCV_FILE} -w),)
ifneq ($(EXTERNAL_INTERRUPT),no) ifneq ($(EXTERNAL_INTERRUPT),no)
ADDCFLAGS += -CFLAGS -DEXTERNAL_INTERRUPT ADDCFLAGS += -CFLAGS -DEXTERNAL_INTERRUPT
endif endif
@ -267,10 +269,9 @@ all: clean run
run: compile run: compile
./obj_dir/VVexRiscv ./obj_dir/VVexRiscv
verilate: ../../../../VexRiscv.v verilate: ${VEXRISCV_FILE}
rm -f VexRiscv.v*.bin cp ${VEXRISCV_FILE}*.bin . | true
cp ../../../../VexRiscv.v*.bin . | true verilator -cc ${VEXRISCV_FILE} -O3 -CFLAGS -std=c++11 -LDFLAGS -pthread ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-UNOPTFLAT -Wno-WIDTH --x-assign unique --exe main.cpp
verilator -cc ../../../../VexRiscv.v -O3 -CFLAGS -std=c++11 -LDFLAGS -pthread ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-UNOPTFLAT -Wno-WIDTH --x-assign unique --exe main.cpp
compile: verilate compile: verilate
make -j${THREAD_COUNT} -C obj_dir/ -f VVexRiscv.mk VVexRiscv make -j${THREAD_COUNT} -C obj_dir/ -f VVexRiscv.mk VVexRiscv

216
src/test/scala/vexriscv/TestIndividualFeatures.scala
View File

@ -1,9 +1,10 @@
package vexriscv package vexriscv
import java.io.File import java.io.{File, OutputStream}
import java.util.concurrent.TimeUnit
import org.apache.commons.io.FileUtils import org.apache.commons.io.FileUtils
import org.scalatest.FunSuite import org.scalatest.{BeforeAndAfterAll, FunSuite, ParallelTestExecution, Tag, Transformer}
import spinal.core._ import spinal.core._
import vexriscv.demo._ import vexriscv.demo._
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
@ -11,6 +12,8 @@ import vexriscv.plugin._
import scala.collection.mutable import scala.collection.mutable
import scala.collection.mutable.ArrayBuffer import scala.collection.mutable.ArrayBuffer
import scala.concurrent.duration.Duration
import scala.concurrent.{Await, ExecutionContext, Future}
import scala.sys.process._ import scala.sys.process._
import scala.util.Random import scala.util.Random
@ -313,7 +316,7 @@ class SrcDimension extends VexRiscvDimension("Src") {
} }
class IBusDimension extends VexRiscvDimension("IBus") { class IBusDimension(rvcRate : Double) extends VexRiscvDimension("IBus") {
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = { override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
@ -322,7 +325,7 @@ class IBusDimension extends VexRiscvDimension("IBus") {
if(r.nextDouble() < 0.5){ if(r.nextDouble() < 0.5){
val latency = r.nextInt(5) + 1 val latency = r.nextInt(5) + 1
val compressed = r.nextBoolean() val compressed = r.nextDouble() < rvcRate
val injectorStage = r.nextBoolean() || latency == 1 val injectorStage = r.nextBoolean() || latency == 1
val prediction = random(r, List(NONE, STATIC, DYNAMIC, DYNAMIC_TARGET)) val prediction = random(r, List(NONE, STATIC, DYNAMIC, DYNAMIC_TARGET))
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL) val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
@ -345,7 +348,7 @@ class IBusDimension extends VexRiscvDimension("IBus") {
} }
} else { } else {
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL) val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
val compressed = r.nextBoolean() val compressed = r.nextDouble() < rvcRate
val tighlyCoupled = r.nextBoolean() && !catchAll val tighlyCoupled = r.nextBoolean() && !catchAll
// val tighlyCoupled = false // val tighlyCoupled = false
val prediction = random(r, List(NONE, STATIC, DYNAMIC, DYNAMIC_TARGET)) val prediction = random(r, List(NONE, STATIC, DYNAMIC, DYNAMIC_TARGET))
@ -497,14 +500,14 @@ class MmuDimension extends VexRiscvDimension("DBus") {
trait CatchAllPosition trait CatchAllPosition
class CsrDimension(freertos : String, zephyr : String) extends VexRiscvDimension("Csr") { class CsrDimension(freertos : String, zephyr : String, linux : String) extends VexRiscvDimension("Csr") {
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = { override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL) val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
val supervisor = universes.contains(VexRiscvUniverse.SUPERVISOR) val supervisor = universes.contains(VexRiscvUniverse.SUPERVISOR)
if(supervisor){ if(supervisor){
new VexRiscvPosition("Supervisor") with CatchAllPosition{ new VexRiscvPosition("Supervisor") with CatchAllPosition{
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.linuxFull(0x80000020l)) override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.linuxFull(0x80000020l))
override def testParam = s"FREERTOS=$freertos ZEPHYR=$zephyr LINUX_REGRESSION=${sys.env.getOrElse("VEXRISCV_REGRESSION_LINUX_REGRESSION", "yes")} SUPERVISOR=yes" override def testParam = s"FREERTOS=$freertos ZEPHYR=$zephyr LINUX_REGRESSION=$linux SUPERVISOR=yes"
} }
} else if(catchAll){ } else if(catchAll){
new VexRiscvPosition("MachineOs") with CatchAllPosition{ new VexRiscvPosition("MachineOs") with CatchAllPosition{
@ -534,6 +537,7 @@ class DebugDimension extends VexRiscvDimension("Debug") {
}, },
new VexRiscvPosition("Enable") { new VexRiscvPosition("Enable") {
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))) override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset")))
override def testParam = "CONCURRENT_OS_EXECUTIONS=yes"
} }
)) ))
} }
@ -553,32 +557,100 @@ class DecoderDimension extends VexRiscvDimension("Decoder") {
} }
} }
object PlayFuture extends App{
implicit val ec = ExecutionContext.global
val x = for(i <- 0 until 160) yield Future {
print(s"$i ")
class TestIndividualFeatures extends FunSuite { Thread.sleep(1000)
def doCmd(cmd: String): String = {
val stdOut = new StringBuilder()
class Logger extends ProcessLogger {
override def err(s: => String): Unit = {
if (!s.startsWith("ar: creating ")) println(s)
}
override def out(s: => String): Unit = {
println(s)
stdOut ++= s
}
override def buffer[T](f: => T) = f
}
Process(cmd, new File("src/test/cpp/regression")).!(new Logger)
stdOut.toString()
} }
Thread.sleep(8000)
}
class MultithreadedFunSuite extends FunSuite {
implicit val ec = ExecutionContext.global
class Job(body : => Unit){
val originalOutput = Console.out
val buffer = mutable.Queue[Char]()
var bufferEnabled = true
def redirector() = new OutputStream{
override def write(i: Int): Unit = synchronized {
if(bufferEnabled) buffer += i.toChar
else originalOutput.print(i.toChar)
}
}
val future = Future{
Console.withOut(redirector()){
Console.withErr(redirector())(body)
}
}
def join(): Unit = {
Thread.sleep(50)
synchronized{
bufferEnabled = false
buffer.foreach(originalOutput.print)
}
Await.result(future, Duration.Inf)
}
}
override protected def test(testName: String, testTags: Tag*)(testFun: => Unit) {
val job = new Job(testFun)
super.test(testName, testTags :_*)(job.join())
}
protected def testSingleThread(testName: String, testTags: Tag*)(testFun: => Unit) {
super.test(testName, testTags :_*)(testFun)
}
}
class FunTestPara extends MultithreadedFunSuite{
def createTest(name : String): Unit ={
test(name){
for(i <- 0 to 4) {
println(s"$name $i")
Thread.sleep(500)
}
}
}
(0 to 80).map(_.toString).foreach(createTest)
}
class FunTestPlay extends FunSuite {
def createTest(name : String): Unit ={
test(name){
Thread.sleep(500)
for(i <- 0 to 4) {
println(s"$name $i")
Thread.sleep(500)
}
}
}
(0 to 80).map(_.toString).foreach(createTest)
}
class TestIndividualFeatures extends MultithreadedFunSuite {
val testCount = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_COUNT", "100").toInt
val seed = sys.env.getOrElse("VEXRISCV_REGRESSION_SEED", Random.nextLong().toString).toLong
val testId : Set[Int] = sys.env.get("VEXRISCV_REGRESSION_TEST_ID") match {
case Some(x) if x != "" => x.split(',').map(_.toInt).toSet
case _ => (0 until testCount).toSet
}
val rvcRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_RVC_RATE", "0.5").toDouble
val linuxRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_LINUX_RATE", "0.3").toDouble
val machineOsRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE", "0.5").toDouble
val linuxRegression = sys.env.getOrElse("VEXRISCV_REGRESSION_LINUX_REGRESSION", "yes")
val coremarkRegression = sys.env.getOrElse("VEXRISCV_REGRESSION_COREMARK", "yes")
val zephyrCount = sys.env.getOrElse("VEXRISCV_REGRESSION_ZEPHYR_COUNT", "4")
val demwRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_DEMW_RATE", "0.6").toDouble
val demRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_DEM_RATE", "0.5").toDouble
val lock = new{}
val dimensions = List( val dimensions = List(
new IBusDimension, new IBusDimension(rvcRate),
new DBusDimension, new DBusDimension,
new MulDivDimension, new MulDivDimension,
new ShiftDimension, new ShiftDimension,
@ -586,18 +658,46 @@ class TestIndividualFeatures extends FunSuite {
new HazardDimension, new HazardDimension,
new RegFileDimension, new RegFileDimension,
new SrcDimension, new SrcDimension,
new CsrDimension(/*sys.env.getOrElse("VEXRISCV_REGRESSION_FREERTOS_COUNT", "1")*/ "0", sys.env.getOrElse("VEXRISCV_REGRESSION_ZEPHYR_COUNT", "4")), //Freertos old port software is broken new CsrDimension(/*sys.env.getOrElse("VEXRISCV_REGRESSION_FREERTOS_COUNT", "1")*/ "0", zephyrCount, linuxRegression), //Freertos old port software is broken
new DecoderDimension, new DecoderDimension,
new DebugDimension, new DebugDimension,
new MmuDimension new MmuDimension
) )
var clockCounter = 0l
var startAt = System.currentTimeMillis()
def doTest(positionsToApply : List[VexRiscvPosition], prefix : String = "", testSeed : Int, universes : mutable.HashSet[VexRiscvUniverse]): Unit ={ def doTest(positionsToApply : List[VexRiscvPosition], prefix : String = "", testSeed : Int, universes : mutable.HashSet[VexRiscvUniverse]): Unit ={
val noMemory = universes.contains(VexRiscvUniverse.NO_MEMORY) val noMemory = universes.contains(VexRiscvUniverse.NO_MEMORY)
val noWriteback = universes.contains(VexRiscvUniverse.NO_WRITEBACK) val noWriteback = universes.contains(VexRiscvUniverse.NO_WRITEBACK)
def gen = { val name = (if(noMemory) "noMemoryStage_" else "") + (if(noWriteback) "noWritebackStage_" else "") + positionsToApply.map(d => d.dimension.name + "_" + d.name).mkString("_")
val workspace = "simWorkspace"
val project = s"$workspace/$prefix"
def doCmd(cmd: String): String = {
val stdOut = new StringBuilder()
class Logger extends ProcessLogger {
override def err(s: => String): Unit = {
if (!s.startsWith("ar: creating ")) println(s)
}
override def out(s: => String): Unit = {
println(s)
stdOut ++= s
}
override def buffer[T](f: => T) = f
}
Process(cmd, new File(project)).!(new Logger)
stdOut.toString()
}
test(prefix + name) {
println("START TEST " + prefix + name)
//Cleanup
FileUtils.deleteDirectory(new File(project))
FileUtils.forceMkdir(new File(project))
//Generate RTL
FileUtils.deleteQuietly(new File("VexRiscv.v")) FileUtils.deleteQuietly(new File("VexRiscv.v"))
SpinalVerilog{ SpinalConfig(targetDirectory = project).generateVerilog{
val config = VexRiscvConfig( val config = VexRiscvConfig(
withMemoryStage = !noMemory, withMemoryStage = !noMemory,
withWriteBackStage = !noWriteback, withWriteBackStage = !noWriteback,
@ -609,63 +709,52 @@ class TestIndividualFeatures extends FunSuite {
for (positionToApply <- positionsToApply) positionToApply.applyOn(config) for (positionToApply <- positionsToApply) positionToApply.applyOn(config)
new VexRiscv(config) new VexRiscv(config)
} }
}
val name = (if(noMemory) "noMemoryStage_" else "") + (if(noWriteback) "noWritebackStage_" else "") + positionsToApply.map(d => d.dimension.name + "_" + d.name).mkString("_") //Setup test
test(prefix + name + "_gen") { val files = List("main.cpp", "encoding.h" ,"makefile", "dhrystoneO3.logRef", "dhrystoneO3C.logRef","dhrystoneO3MC.logRef","dhrystoneO3M.logRef")
gen files.foreach(f => FileUtils.copyFileToDirectory(new File(s"src/test/cpp/regression/$f"), new File(project)))
}
//Test RTL
test(prefix + name + "_test") {
println("START TEST " + prefix + name)
val debug = true val debug = true
val stdCmd = (s"make clean run WITH_USER_IO=no REDO=10 TRACE=${if(debug) "yes" else "no"} TRACE_START=9999924910246l FLOW_INFO=no STOP_ON_ERROR=no DHRYSTONE=yes COREMARK=${sys.env.getOrElse("VEXRISCV_REGRESSION_COREMARK", "yes")} THREAD_COUNT=${sys.env.getOrElse("VEXRISCV_REGRESSION_THREAD_COUNT", 1)} ") + s" SEED=${testSeed} " val stdCmd = (s"make run REGRESSION_PATH=../../src/test/cpp/regression VEXRISCV_FILE=VexRiscv.v WITH_USER_IO=no REDO=10 TRACE=${if(debug) "yes" else "no"} TRACE_START=1000000000000l STOP_ON_ERROR=no FLOW_INFO=no STOP_ON_ERROR=no DHRYSTONE=yes COREMARK=${coremarkRegression} THREAD_COUNT=1 ") + s" SEED=${testSeed} "
val testCmd = stdCmd + (positionsToApply).map(_.testParam).mkString(" ") val testCmd = stdCmd + (positionsToApply).map(_.testParam).mkString(" ")
println(testCmd) println(testCmd)
val str = doCmd(testCmd) val str = doCmd(testCmd)
assert(str.contains("REGRESSION SUCCESS") && !str.contains("Broken pipe")) assert(str.contains("REGRESSION SUCCESS") && !str.contains("Broken pipe"))
val pattern = "Had simulate ([0-9]+)".r
val hit = pattern.findFirstMatchIn(str)
lock.synchronized(clockCounter += hit.get.group(1).toLong)
} }
} }
var testId : Option[mutable.HashSet[Int]] = None
var seed = sys.env.getOrElse("VEXRISCV_REGRESSION_SEED", Random.nextInt(1000000000).toString).toLong
// val testId = Some(mutable.HashSet(3,4,9,11,13,16,18,19,20,21))
// val testId = Some(mutable.HashSet(15))
// seed = -7374992264756372315l
// testId = Some(mutable.HashSet(1,2,6,14,15,16,19))
// testId = Some(mutable.HashSet(1,2,6,14))
// testId = Some(mutable.HashSet(1))
val rand = new Random(seed) val rand = new Random(seed)
test("Info"){ test("Info"){
println(s"MAIN_SEED=$seed") println(s"MAIN_SEED=$seed")
} }
println(s"Seed=$seed") println(s"Seed=$seed")
for(i <- 0 until sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_COUNT", "100").toInt){ for(i <- 0 until testCount){
var positions : List[VexRiscvPosition] = null var positions : List[VexRiscvPosition] = null
var universe = mutable.HashSet[VexRiscvUniverse]() var universe = mutable.HashSet[VexRiscvUniverse]()
if(rand.nextDouble() < 0.5) universe += VexRiscvUniverse.EXECUTE_RF if(rand.nextDouble() < 0.5) universe += VexRiscvUniverse.EXECUTE_RF
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_LINUX_RATE", "0.3").toDouble > rand.nextDouble()) { if(linuxRate > rand.nextDouble()) {
universe += VexRiscvUniverse.CATCH_ALL universe += VexRiscvUniverse.CATCH_ALL
universe += VexRiscvUniverse.MMU universe += VexRiscvUniverse.MMU
universe += VexRiscvUniverse.FORCE_MULDIV universe += VexRiscvUniverse.FORCE_MULDIV
universe += VexRiscvUniverse.SUPERVISOR universe += VexRiscvUniverse.SUPERVISOR
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_DEMW_RATE", "0.6").toDouble < rand.nextDouble()){ if(demwRate < rand.nextDouble()){
universe += VexRiscvUniverse.NO_WRITEBACK universe += VexRiscvUniverse.NO_WRITEBACK
} }
} else { } else {
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE", "0.5").toDouble > rand.nextDouble()) { if(machineOsRate > rand.nextDouble()) {
universe += VexRiscvUniverse.CATCH_ALL universe += VexRiscvUniverse.CATCH_ALL
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_DEMW_RATE", "0.6").toDouble < rand.nextDouble()){ if(demwRate < rand.nextDouble()){
universe += VexRiscvUniverse.NO_WRITEBACK universe += VexRiscvUniverse.NO_WRITEBACK
} }
} }
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_DEMW_RATE", "0.6").toDouble > rand.nextDouble()){ if(demwRate > rand.nextDouble()){
}else if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_DEM_RATE", "0.5").toDouble > rand.nextDouble()){ }else if(demRate > rand.nextDouble()){
universe += VexRiscvUniverse.NO_WRITEBACK universe += VexRiscvUniverse.NO_WRITEBACK
} else { } else {
universe += VexRiscvUniverse.NO_WRITEBACK universe += VexRiscvUniverse.NO_WRITEBACK
@ -678,8 +767,13 @@ class TestIndividualFeatures extends FunSuite {
}while(!positions.forall(_.isCompatibleWith(positions))) }while(!positions.forall(_.isCompatibleWith(positions)))
val testSeed = rand.nextInt() val testSeed = rand.nextInt()
if(testId.isEmpty || testId.get.contains(i)) if(testId.contains(i))
doTest(positions," random_" + i + "_", testSeed, universe) doTest(positions,"test_id_" + i + "_", testSeed, universe)
Hack.dCounter += 1 Hack.dCounter += 1
} }
testSingleThread("report"){
val time = (System.currentTimeMillis() - startAt)*1e-3
val clockPerSecond = (clockCounter/time*1e-3).toLong
println(s"Duration=${(time/60).toInt}mn clocks=${(clockCounter*1e-6).toLong}M clockPerSecond=${clockPerSecond}K")
}
} }