Merge branch 'dev' into rework_fetch
# Conflicts: # src/test/scala/vexriscv/TestIndividualFeatures.scala
This commit is contained in:
commit
78d4660282
45
README.md
45
README.md
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@ -185,24 +185,47 @@ NOTES:
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[![Build Status](https://travis-ci.org/SpinalHDL/VexRiscv.svg?branch=master)](https://travis-ci.org/SpinalHDL/VexRiscv)
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To run tests (need the verilator simulator), go in the src/test/cpp/regression folder and run :
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To run tests (need java, scala, verilator), just do :
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```sh
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# To test the GenFull CPU
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# (Don't worry about the CSR test not passing, basicaly the GenFull isn't the truly full version of the CPU, some CSR features are disable in it)
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make clean run
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# To test the GenSmallest CPU
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make clean run IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no
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export VEXRISCV_REGRESSION_SEED=42
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export VEXRISCV_REGRESSION_TEST_ID=
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sbt "testOnly vexriscv.TestIndividualFeatures"
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```
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The self-test includes:
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- ISA tests from https://github.com/riscv/riscv-tests/tree/master/isa
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This will generate random VexRiscv configuration and test them with:
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- ISA tests from https://github.com/riscv/riscv-tests/tree/master/isa and https://github.com/riscv/riscv-compliance
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- Dhrystone benchmark
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- 24 FreeRTOS tests
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- Coremark benchmark
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- Zephyr os
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- Buildroot/Linux os
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- Some handwritten tests to check the CSR, debug module and MMU plugins
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You can enable FreeRTOS tests by adding `FREERTOS=yes` to the command line, but it will take time to run. Also, it uses THREAD_COUNT host CPU threads to run multiple regression in parallel.
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You can rerun some specific test by setting VEXRISCV_REGRESSION_TEST_ID by their id. For instance, if you want to rerun :
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- test_id_5_test_IBus_CachedS1024W1BPL32Relaxvexriscv.plugin.DYNAMIC_DBus_CachedS8192W2BPL16_MulDiv_MulDivFpga_Shift_FullLate_Branch_Late_Hazard_BypassAll_RegFile_SyncDR_Src__Csr_AllNoException_Decoder__Debug_None_DBus_NoMmu
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- test_id_9_test_IBus_Simple1S2InjStagevexriscv.plugin.STATIC_DBus_SimpleLate_MulDiv_MulDivFpgaSimple_Shift_FullEarly_Branch_Late_Hazard_Interlock_RegFile_AsyncER_Src_AddSubExecute_Csr_None_Decoder__Debug_None_DBus_NoMmu
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then :
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```
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export VEXRISCV_REGRESSION_TEST_ID=5,9
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```
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Also there is a few environnement variable that you can use to modulate the random generation :
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| Parameters | range | description |
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| ------------------------------------------- | ------------------ | ----------- |
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| VEXRISCV_REGRESSION_SEED | Int | Seed used to generate the random configurations |
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| VEXRISCV_REGRESSION_TEST_ID | \[Int\[,\Int\]\*\] | Random configuration that should be keeped and tested |
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| VEXRISCV_REGRESSION_CONFIG_COUNT | Int | Number of random configurations |
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| VEXRISCV_REGRESSION_CONFIG_RVC_RATE | 0.0-1.0 | Chance to generate a RVC config |
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| VEXRISCV_REGRESSION_CONFIG_LINUX_RATE | 0.0-1.0 | Chance to generate a linux ready config |
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| VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE | 0.0-1.0 | Chance to generate a machine mode OS ready config |
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| VEXRISCV_REGRESSION_LINUX_REGRESSION | yes/no | Enable the linux test |
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| VEXRISCV_REGRESSION_COREMARK | yes/no | Enable the Coremark test |
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| VEXRISCV_REGRESSION_ZEPHYR_COUNT | Int | Number of zephyr tests to run on capable configs |
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| VEXRISCV_REGRESSION_CONFIG_DEMW_RATE | 0.0-1.0 | Chance to generate a config with writeback stage |
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| VEXRISCV_REGRESSION_CONFIG_DEM_RATE | 0.0-1.0 | Chance to generate a config with memory stage |
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## Interactive debug of the simulated CPU via GDB OpenOCD and Verilator
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It's as described to run tests, but you just have to add `DEBUG_PLUGIN_EXTERNAL=yes` in the make arguments.
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@ -2805,7 +2805,7 @@ public:
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uint32_t regFileWriteRefIndex = 0;
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TestA() : WorkspaceRegression("testA") {
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loadHex("../../resources/hex/testA.hex");
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loadHex(string(REGRESSION_PATH) + "../../resources/hex/testA.hex");
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}
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virtual void checks(){
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@ -2831,7 +2831,7 @@ public:
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TestX28(string name, uint32_t *ref, uint32_t refSize) : WorkspaceRegression(name) {
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this->ref = ref;
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this->refSize = refSize;
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loadHex("../../resources/hex/" + name + ".hex");
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loadHex(string(REGRESSION_PATH) + "../../resources/hex/" + name + ".hex");
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}
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virtual void checks(){
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@ -2851,7 +2851,7 @@ public:
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class RiscvTest : public WorkspaceRegression{
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public:
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RiscvTest(string name) : WorkspaceRegression(name) {
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loadHex("../../resources/hex/" + name + ".hex");
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loadHex(string(REGRESSION_PATH) + "../../resources/hex/" + name + ".hex");
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bootAt(0x800000bcu);
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}
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@ -2899,7 +2899,7 @@ public:
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setIStall(iStall);
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setDStall(dStall);
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withRiscvRef();
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loadHex("../../resources/hex/" + hexName + ".hex");
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loadHex(string(REGRESSION_PATH) + "../../resources/hex/" + hexName + ".hex");
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this->hexName = hexName;
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}
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@ -2942,7 +2942,7 @@ public:
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int out32Counter = 0;
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Compliance(string name) : WorkspaceRegression(name) {
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withRiscvRef();
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loadHex("../../resources/hex/" + name + ".elf.hex");
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loadHex(string(REGRESSION_PATH) + "../../resources/hex/" + name + ".elf.hex");
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out32.open (name + ".out32");
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this->name = name;
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}
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@ -2963,7 +2963,7 @@ public:
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virtual void pass(){
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FILE *refFile = fopen((string("../../resources/ref/") + name + ".reference_output").c_str(), "r");
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FILE *refFile = fopen((string(REGRESSION_PATH) + string("../../resources/ref/") + name + ".reference_output").c_str(), "r");
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fseek(refFile, 0, SEEK_END);
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uint32_t refSize = ftell(refFile);
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fseek(refFile, 0, SEEK_SET);
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@ -3152,7 +3152,7 @@ public:
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DebugPluginTest() : WorkspaceRegression("DebugPluginTest") {
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loadHex("../../resources/hex/debugPlugin.hex");
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loadHex(string(REGRESSION_PATH) + "../../resources/hex/debugPlugin.hex");
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pthread_create(&clientThreadId, NULL, &clientThreadWrapper, this);
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}
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@ -3837,17 +3837,17 @@ int main(int argc, char **argv, char **env) {
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// #endif
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#ifdef IBUS_CACHED
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redo(REDO,WorkspaceRegression("icache").withRiscvRef()->loadHex("../raw/icache/build/icache.hex")->bootAt(0x80000000u)->run(50e3););
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redo(REDO,WorkspaceRegression("icache").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../raw/icache/build/icache.hex")->bootAt(0x80000000u)->run(50e3););
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#endif
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#ifdef DBUS_CACHED
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redo(REDO,WorkspaceRegression("dcache").loadHex("../raw/dcache/build/dcache.hex")->bootAt(0x80000000u)->run(2500e3););
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redo(REDO,WorkspaceRegression("dcache").loadHex(string(REGRESSION_PATH) + "../raw/dcache/build/dcache.hex")->bootAt(0x80000000u)->run(2500e3););
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#endif
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#ifdef MMU
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redo(REDO,WorkspaceRegression("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
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redo(REDO,WorkspaceRegression("mmu").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
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#endif
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#ifdef SUPERVISOR
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redo(REDO,WorkspaceRegression("deleg").withRiscvRef()->loadHex("../raw/deleg/build/deleg.hex")->bootAt(0x80000000u)->run(50e3););
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redo(REDO,WorkspaceRegression("deleg").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../raw/deleg/build/deleg.hex")->bootAt(0x80000000u)->run(50e3););
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#endif
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#ifdef DEBUG_PLUGIN
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@ -3858,20 +3858,20 @@ int main(int argc, char **argv, char **env) {
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#endif
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#ifdef CUSTOM_SIMD_ADD
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redo(REDO,WorkspaceRegression("custom_simd_add").loadHex("../custom/simd_add/build/custom_simd_add.hex")->bootAt(0x00000000u)->run(50e3););
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redo(REDO,WorkspaceRegression("custom_simd_add").loadHex(string(REGRESSION_PATH) + "../custom/simd_add/build/custom_simd_add.hex")->bootAt(0x00000000u)->run(50e3););
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#endif
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#ifdef CUSTOM_CSR
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redo(REDO,WorkspaceRegression("custom_csr").loadHex("../custom/custom_csr/build/custom_csr.hex")->bootAt(0x00000000u)->run(50e3););
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redo(REDO,WorkspaceRegression("custom_csr").loadHex(string(REGRESSION_PATH) + "../custom/custom_csr/build/custom_csr.hex")->bootAt(0x00000000u)->run(50e3););
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#endif
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#ifdef LRSC
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redo(REDO,WorkspaceRegression("lrsc").withRiscvRef()->loadHex("../raw/lrsc/build/lrsc.hex")->bootAt(0x00000000u)->run(10e3););
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redo(REDO,WorkspaceRegression("lrsc").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../raw/lrsc/build/lrsc.hex")->bootAt(0x00000000u)->run(10e3););
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#endif
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#ifdef AMO
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redo(REDO,WorkspaceRegression("amo").withRiscvRef()->loadHex("../raw/amo/build/amo.hex")->bootAt(0x00000000u)->run(10e3););
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redo(REDO,WorkspaceRegression("amo").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../raw/amo/build/amo.hex")->bootAt(0x00000000u)->run(10e3););
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#endif
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#ifdef DHRYSTONE
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@ -3910,7 +3910,7 @@ int main(int argc, char **argv, char **env) {
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if(withStall == -1) break;
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#endif
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WorkspaceRegression("coremark_" + rv + (withStall > 0 ? "_stall" : "_nostall")).withRiscvRef()
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->loadBin("../../resources/bin/coremark_" + rv + ".bin", 0x80000000)
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->loadBin(string(REGRESSION_PATH) + "../../resources/bin/coremark_" + rv + ".bin", 0x80000000)
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->bootAt(0x80000000)
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->setIStall(withStall > 0)
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->setDStall(withStall > 0)
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@ -3930,17 +3930,17 @@ int main(int argc, char **argv, char **env) {
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/*for(int redo = 0;redo < 4;redo++)*/{
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for(const string &name : freeRtosTests){
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tasks.push_back([=]() { WorkspaceRegression(name + "_rv32i_O0").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32i_O0.hex")->bootAt(0x80000000u)->run(4e6*15);});
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tasks.push_back([=]() { WorkspaceRegression(name + "_rv32i_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32i_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
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tasks.push_back([=]() { WorkspaceRegression(name + "_rv32i_O0").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/freertos/" + name + "_rv32i_O0.hex")->bootAt(0x80000000u)->run(4e6*15);});
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tasks.push_back([=]() { WorkspaceRegression(name + "_rv32i_O3").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/freertos/" + name + "_rv32i_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
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#ifdef COMPRESSED
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// tasks.push_back([=]() { WorkspaceRegression(name + "_rv32ic_O0").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32ic_O0.hex")->bootAt(0x80000000u)->run(5e6*15);});
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tasks.push_back([=]() { WorkspaceRegression(name + "_rv32ic_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32ic_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
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// tasks.push_back([=]() { WorkspaceRegression(name + "_rv32ic_O0").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/freertos/" + name + "_rv32ic_O0.hex")->bootAt(0x80000000u)->run(5e6*15);});
|
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tasks.push_back([=]() { WorkspaceRegression(name + "_rv32ic_O3").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/freertos/" + name + "_rv32ic_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
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#endif
|
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#if defined(MUL) && defined(DIV)
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||||
// #ifdef COMPRESSED
|
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// tasks.push_back([=]() { WorkspaceRegression(name + "_rv32imac_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32imac_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
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// tasks.push_back([=]() { WorkspaceRegression(name + "_rv32imac_O3").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/freertos/" + name + "_rv32imac_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
|
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// #else
|
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tasks.push_back([=]() { WorkspaceRegression(name + "_rv32im_O3").withRiscvRef()->loadHex("../../resources/freertos/" + name + "_rv32im_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
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tasks.push_back([=]() { WorkspaceRegression(name + "_rv32im_O3").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/freertos/" + name + "_rv32im_O3.hex")->bootAt(0x80000000u)->run(4e6*15);});
|
||||
// #endif
|
||||
#endif
|
||||
}
|
||||
|
@ -3967,12 +3967,12 @@ int main(int argc, char **argv, char **env) {
|
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/*for(int redo = 0;redo < 4;redo++)*/{
|
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for(const string &name : zephyrTests){
|
||||
#ifdef COMPRESSED
|
||||
tasks.push_back([=]() { ZephyrRegression(name + "_rv32ic").withRiscvRef()->loadHex("../../resources/VexRiscvRegressionData/sim/zephyr/" + name + "_rv32ic.hex")->bootAt(0x80000000u)->run(180e6);});
|
||||
tasks.push_back([=]() { ZephyrRegression(name + "_rv32ic").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/VexRiscvRegressionData/sim/zephyr/" + name + "_rv32ic.hex")->bootAt(0x80000000u)->run(180e6);});
|
||||
#else
|
||||
tasks.push_back([=]() { ZephyrRegression(name + "_rv32i").withRiscvRef()->loadHex("../../resources/VexRiscvRegressionData/sim/zephyr/" + name + "_rv32i.hex")->bootAt(0x80000000u)->run(180e6);});
|
||||
tasks.push_back([=]() { ZephyrRegression(name + "_rv32i").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/VexRiscvRegressionData/sim/zephyr/" + name + "_rv32i.hex")->bootAt(0x80000000u)->run(180e6);});
|
||||
#endif
|
||||
#if defined(MUL) && defined(DIV)
|
||||
tasks.push_back([=]() { ZephyrRegression(name + "_rv32im").withRiscvRef()->loadHex("../../resources/VexRiscvRegressionData/sim/zephyr/" + name + "_rv32im.hex")->bootAt(0x80000000u)->run(180e6);});
|
||||
tasks.push_back([=]() { ZephyrRegression(name + "_rv32im").withRiscvRef()->loadHex(string(REGRESSION_PATH) + "../../resources/VexRiscvRegressionData/sim/zephyr/" + name + "_rv32im.hex")->bootAt(0x80000000u)->run(180e6);});
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
@ -3993,10 +3993,10 @@ int main(int argc, char **argv, char **env) {
|
|||
LinuxRegression soc("linux");
|
||||
#ifndef DEBUG_PLUGIN_EXTERNAL
|
||||
soc.withRiscvRef();
|
||||
soc.loadBin(EMULATOR, 0x80000000);
|
||||
soc.loadBin(VMLINUX, 0xC0000000);
|
||||
soc.loadBin(DTB, 0xC3000000);
|
||||
soc.loadBin(RAMDISK, 0xC2000000);
|
||||
soc.loadBin(string(REGRESSION_PATH) + EMULATOR, 0x80000000);
|
||||
soc.loadBin(string(REGRESSION_PATH) + VMLINUX, 0xC0000000);
|
||||
soc.loadBin(string(REGRESSION_PATH) + DTB, 0xC3000000);
|
||||
soc.loadBin(string(REGRESSION_PATH) + RAMDISK, 0xC2000000);
|
||||
#endif
|
||||
//soc.setIStall(true);
|
||||
//soc.setDStall(true);
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
DEBUG?=no
|
||||
|
||||
REGRESSION_PATH?=./
|
||||
VEXRISCV_FILE?=../../../../VexRiscv.v
|
||||
IBUS?=CACHED
|
||||
IBUS_TC?=no
|
||||
DBUS?=CACHED
|
||||
|
@ -38,6 +39,7 @@ STOP_ON_ERROR?=no
|
|||
COREMARK=no
|
||||
WITH_USER_IO?=no
|
||||
|
||||
ADDCFLAGS += -CFLAGS -DREGRESSION_PATH='\"$(REGRESSION_PATH)/\"'
|
||||
ADDCFLAGS += -CFLAGS -DIBUS_${IBUS}
|
||||
ADDCFLAGS += -CFLAGS -DDBUS_${DBUS}
|
||||
ADDCFLAGS += -CFLAGS -DREDO=${REDO}
|
||||
|
@ -107,11 +109,11 @@ endif
|
|||
|
||||
|
||||
|
||||
ifneq ($(shell grep timerInterrupt ../../../../VexRiscv.v -w),)
|
||||
ifneq ($(shell grep timerInterrupt ${VEXRISCV_FILE} -w),)
|
||||
ADDCFLAGS += -CFLAGS -DTIMER_INTERRUPT
|
||||
endif
|
||||
|
||||
ifneq ($(shell grep externalInterrupt ../../../../VexRiscv.v -w),)
|
||||
ifneq ($(shell grep externalInterrupt ${VEXRISCV_FILE} -w),)
|
||||
ifneq ($(EXTERNAL_INTERRUPT),no)
|
||||
ADDCFLAGS += -CFLAGS -DEXTERNAL_INTERRUPT
|
||||
endif
|
||||
|
@ -267,10 +269,9 @@ all: clean run
|
|||
run: compile
|
||||
./obj_dir/VVexRiscv
|
||||
|
||||
verilate: ../../../../VexRiscv.v
|
||||
rm -f VexRiscv.v*.bin
|
||||
cp ../../../../VexRiscv.v*.bin . | true
|
||||
verilator -cc ../../../../VexRiscv.v -O3 -CFLAGS -std=c++11 -LDFLAGS -pthread ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-UNOPTFLAT -Wno-WIDTH --x-assign unique --exe main.cpp
|
||||
verilate: ${VEXRISCV_FILE}
|
||||
cp ${VEXRISCV_FILE}*.bin . | true
|
||||
verilator -cc ${VEXRISCV_FILE} -O3 -CFLAGS -std=c++11 -LDFLAGS -pthread ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-UNOPTFLAT -Wno-WIDTH --x-assign unique --exe main.cpp
|
||||
|
||||
compile: verilate
|
||||
make -j${THREAD_COUNT} -C obj_dir/ -f VVexRiscv.mk VVexRiscv
|
||||
|
|
|
@ -1,9 +1,10 @@
|
|||
package vexriscv
|
||||
|
||||
import java.io.File
|
||||
import java.io.{File, OutputStream}
|
||||
import java.util.concurrent.TimeUnit
|
||||
|
||||
import org.apache.commons.io.FileUtils
|
||||
import org.scalatest.FunSuite
|
||||
import org.scalatest.{BeforeAndAfterAll, FunSuite, ParallelTestExecution, Tag, Transformer}
|
||||
import spinal.core._
|
||||
import vexriscv.demo._
|
||||
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
|
||||
|
@ -11,6 +12,8 @@ import vexriscv.plugin._
|
|||
|
||||
import scala.collection.mutable
|
||||
import scala.collection.mutable.ArrayBuffer
|
||||
import scala.concurrent.duration.Duration
|
||||
import scala.concurrent.{Await, ExecutionContext, Future}
|
||||
import scala.sys.process._
|
||||
import scala.util.Random
|
||||
|
||||
|
@ -313,7 +316,7 @@ class SrcDimension extends VexRiscvDimension("Src") {
|
|||
}
|
||||
|
||||
|
||||
class IBusDimension extends VexRiscvDimension("IBus") {
|
||||
class IBusDimension(rvcRate : Double) extends VexRiscvDimension("IBus") {
|
||||
|
||||
|
||||
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
|
||||
|
@ -322,7 +325,7 @@ class IBusDimension extends VexRiscvDimension("IBus") {
|
|||
|
||||
if(r.nextDouble() < 0.5){
|
||||
val latency = r.nextInt(5) + 1
|
||||
val compressed = r.nextBoolean()
|
||||
val compressed = r.nextDouble() < rvcRate
|
||||
val injectorStage = r.nextBoolean() || latency == 1
|
||||
val prediction = random(r, List(NONE, STATIC, DYNAMIC, DYNAMIC_TARGET))
|
||||
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
|
||||
|
@ -345,7 +348,7 @@ class IBusDimension extends VexRiscvDimension("IBus") {
|
|||
}
|
||||
} else {
|
||||
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
|
||||
val compressed = r.nextBoolean()
|
||||
val compressed = r.nextDouble() < rvcRate
|
||||
val tighlyCoupled = r.nextBoolean() && !catchAll
|
||||
// val tighlyCoupled = false
|
||||
val prediction = random(r, List(NONE, STATIC, DYNAMIC, DYNAMIC_TARGET))
|
||||
|
@ -497,14 +500,14 @@ class MmuDimension extends VexRiscvDimension("DBus") {
|
|||
trait CatchAllPosition
|
||||
|
||||
|
||||
class CsrDimension(freertos : String, zephyr : String) extends VexRiscvDimension("Csr") {
|
||||
class CsrDimension(freertos : String, zephyr : String, linux : String) extends VexRiscvDimension("Csr") {
|
||||
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
|
||||
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
|
||||
val supervisor = universes.contains(VexRiscvUniverse.SUPERVISOR)
|
||||
if(supervisor){
|
||||
new VexRiscvPosition("Supervisor") with CatchAllPosition{
|
||||
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.linuxFull(0x80000020l))
|
||||
override def testParam = s"FREERTOS=$freertos ZEPHYR=$zephyr LINUX_REGRESSION=${sys.env.getOrElse("VEXRISCV_REGRESSION_LINUX_REGRESSION", "yes")} SUPERVISOR=yes"
|
||||
override def testParam = s"FREERTOS=$freertos ZEPHYR=$zephyr LINUX_REGRESSION=$linux SUPERVISOR=yes"
|
||||
}
|
||||
} else if(catchAll){
|
||||
new VexRiscvPosition("MachineOs") with CatchAllPosition{
|
||||
|
@ -534,6 +537,7 @@ class DebugDimension extends VexRiscvDimension("Debug") {
|
|||
},
|
||||
new VexRiscvPosition("Enable") {
|
||||
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset")))
|
||||
override def testParam = "CONCURRENT_OS_EXECUTIONS=yes"
|
||||
}
|
||||
))
|
||||
}
|
||||
|
@ -553,32 +557,100 @@ class DecoderDimension extends VexRiscvDimension("Decoder") {
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
class TestIndividualFeatures extends FunSuite {
|
||||
def doCmd(cmd: String): String = {
|
||||
val stdOut = new StringBuilder()
|
||||
class Logger extends ProcessLogger {
|
||||
override def err(s: => String): Unit = {
|
||||
if (!s.startsWith("ar: creating ")) println(s)
|
||||
object PlayFuture extends App{
|
||||
implicit val ec = ExecutionContext.global
|
||||
val x = for(i <- 0 until 160) yield Future {
|
||||
print(s"$i ")
|
||||
Thread.sleep(1000)
|
||||
}
|
||||
|
||||
override def out(s: => String): Unit = {
|
||||
println(s)
|
||||
stdOut ++= s
|
||||
Thread.sleep(8000)
|
||||
}
|
||||
|
||||
override def buffer[T](f: => T) = f
|
||||
class MultithreadedFunSuite extends FunSuite {
|
||||
implicit val ec = ExecutionContext.global
|
||||
class Job(body : => Unit){
|
||||
val originalOutput = Console.out
|
||||
val buffer = mutable.Queue[Char]()
|
||||
var bufferEnabled = true
|
||||
def redirector() = new OutputStream{
|
||||
override def write(i: Int): Unit = synchronized {
|
||||
if(bufferEnabled) buffer += i.toChar
|
||||
else originalOutput.print(i.toChar)
|
||||
}
|
||||
Process(cmd, new File("src/test/cpp/regression")).!(new Logger)
|
||||
stdOut.toString()
|
||||
}
|
||||
val future = Future{
|
||||
Console.withOut(redirector()){
|
||||
Console.withErr(redirector())(body)
|
||||
}
|
||||
}
|
||||
|
||||
def join(): Unit = {
|
||||
Thread.sleep(50)
|
||||
synchronized{
|
||||
bufferEnabled = false
|
||||
buffer.foreach(originalOutput.print)
|
||||
}
|
||||
Await.result(future, Duration.Inf)
|
||||
}
|
||||
}
|
||||
|
||||
override protected def test(testName: String, testTags: Tag*)(testFun: => Unit) {
|
||||
val job = new Job(testFun)
|
||||
super.test(testName, testTags :_*)(job.join())
|
||||
}
|
||||
protected def testSingleThread(testName: String, testTags: Tag*)(testFun: => Unit) {
|
||||
super.test(testName, testTags :_*)(testFun)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
class FunTestPara extends MultithreadedFunSuite{
|
||||
def createTest(name : String): Unit ={
|
||||
test(name){
|
||||
for(i <- 0 to 4) {
|
||||
println(s"$name $i")
|
||||
Thread.sleep(500)
|
||||
}
|
||||
}
|
||||
}
|
||||
(0 to 80).map(_.toString).foreach(createTest)
|
||||
}
|
||||
|
||||
class FunTestPlay extends FunSuite {
|
||||
def createTest(name : String): Unit ={
|
||||
test(name){
|
||||
Thread.sleep(500)
|
||||
for(i <- 0 to 4) {
|
||||
println(s"$name $i")
|
||||
Thread.sleep(500)
|
||||
}
|
||||
}
|
||||
}
|
||||
(0 to 80).map(_.toString).foreach(createTest)
|
||||
}
|
||||
|
||||
class TestIndividualFeatures extends MultithreadedFunSuite {
|
||||
val testCount = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_COUNT", "100").toInt
|
||||
val seed = sys.env.getOrElse("VEXRISCV_REGRESSION_SEED", Random.nextLong().toString).toLong
|
||||
val testId : Set[Int] = sys.env.get("VEXRISCV_REGRESSION_TEST_ID") match {
|
||||
case Some(x) if x != "" => x.split(',').map(_.toInt).toSet
|
||||
case _ => (0 until testCount).toSet
|
||||
}
|
||||
val rvcRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_RVC_RATE", "0.5").toDouble
|
||||
val linuxRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_LINUX_RATE", "0.3").toDouble
|
||||
val machineOsRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE", "0.5").toDouble
|
||||
val linuxRegression = sys.env.getOrElse("VEXRISCV_REGRESSION_LINUX_REGRESSION", "yes")
|
||||
val coremarkRegression = sys.env.getOrElse("VEXRISCV_REGRESSION_COREMARK", "yes")
|
||||
val zephyrCount = sys.env.getOrElse("VEXRISCV_REGRESSION_ZEPHYR_COUNT", "4")
|
||||
val demwRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_DEMW_RATE", "0.6").toDouble
|
||||
val demRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_DEM_RATE", "0.5").toDouble
|
||||
val lock = new{}
|
||||
|
||||
|
||||
|
||||
val dimensions = List(
|
||||
new IBusDimension,
|
||||
new IBusDimension(rvcRate),
|
||||
new DBusDimension,
|
||||
new MulDivDimension,
|
||||
new ShiftDimension,
|
||||
|
@ -586,18 +658,46 @@ class TestIndividualFeatures extends FunSuite {
|
|||
new HazardDimension,
|
||||
new RegFileDimension,
|
||||
new SrcDimension,
|
||||
new CsrDimension(/*sys.env.getOrElse("VEXRISCV_REGRESSION_FREERTOS_COUNT", "1")*/ "0", sys.env.getOrElse("VEXRISCV_REGRESSION_ZEPHYR_COUNT", "4")), //Freertos old port software is broken
|
||||
new CsrDimension(/*sys.env.getOrElse("VEXRISCV_REGRESSION_FREERTOS_COUNT", "1")*/ "0", zephyrCount, linuxRegression), //Freertos old port software is broken
|
||||
new DecoderDimension,
|
||||
new DebugDimension,
|
||||
new MmuDimension
|
||||
)
|
||||
|
||||
var clockCounter = 0l
|
||||
var startAt = System.currentTimeMillis()
|
||||
def doTest(positionsToApply : List[VexRiscvPosition], prefix : String = "", testSeed : Int, universes : mutable.HashSet[VexRiscvUniverse]): Unit ={
|
||||
val noMemory = universes.contains(VexRiscvUniverse.NO_MEMORY)
|
||||
val noWriteback = universes.contains(VexRiscvUniverse.NO_WRITEBACK)
|
||||
def gen = {
|
||||
val name = (if(noMemory) "noMemoryStage_" else "") + (if(noWriteback) "noWritebackStage_" else "") + positionsToApply.map(d => d.dimension.name + "_" + d.name).mkString("_")
|
||||
val workspace = "simWorkspace"
|
||||
val project = s"$workspace/$prefix"
|
||||
def doCmd(cmd: String): String = {
|
||||
val stdOut = new StringBuilder()
|
||||
class Logger extends ProcessLogger {
|
||||
override def err(s: => String): Unit = {
|
||||
if (!s.startsWith("ar: creating ")) println(s)
|
||||
}
|
||||
override def out(s: => String): Unit = {
|
||||
println(s)
|
||||
stdOut ++= s
|
||||
}
|
||||
override def buffer[T](f: => T) = f
|
||||
}
|
||||
Process(cmd, new File(project)).!(new Logger)
|
||||
stdOut.toString()
|
||||
}
|
||||
|
||||
test(prefix + name) {
|
||||
println("START TEST " + prefix + name)
|
||||
|
||||
//Cleanup
|
||||
FileUtils.deleteDirectory(new File(project))
|
||||
FileUtils.forceMkdir(new File(project))
|
||||
|
||||
//Generate RTL
|
||||
FileUtils.deleteQuietly(new File("VexRiscv.v"))
|
||||
SpinalVerilog{
|
||||
SpinalConfig(targetDirectory = project).generateVerilog{
|
||||
val config = VexRiscvConfig(
|
||||
withMemoryStage = !noMemory,
|
||||
withWriteBackStage = !noWriteback,
|
||||
|
@ -609,63 +709,52 @@ class TestIndividualFeatures extends FunSuite {
|
|||
for (positionToApply <- positionsToApply) positionToApply.applyOn(config)
|
||||
new VexRiscv(config)
|
||||
}
|
||||
}
|
||||
|
||||
val name = (if(noMemory) "noMemoryStage_" else "") + (if(noWriteback) "noWritebackStage_" else "") + positionsToApply.map(d => d.dimension.name + "_" + d.name).mkString("_")
|
||||
test(prefix + name + "_gen") {
|
||||
gen
|
||||
}
|
||||
//Setup test
|
||||
val files = List("main.cpp", "encoding.h" ,"makefile", "dhrystoneO3.logRef", "dhrystoneO3C.logRef","dhrystoneO3MC.logRef","dhrystoneO3M.logRef")
|
||||
files.foreach(f => FileUtils.copyFileToDirectory(new File(s"src/test/cpp/regression/$f"), new File(project)))
|
||||
|
||||
|
||||
test(prefix + name + "_test") {
|
||||
println("START TEST " + prefix + name)
|
||||
//Test RTL
|
||||
val debug = true
|
||||
val stdCmd = (s"make clean run WITH_USER_IO=no REDO=10 TRACE=${if(debug) "yes" else "no"} TRACE_START=9999924910246l FLOW_INFO=no STOP_ON_ERROR=no DHRYSTONE=yes COREMARK=${sys.env.getOrElse("VEXRISCV_REGRESSION_COREMARK", "yes")} THREAD_COUNT=${sys.env.getOrElse("VEXRISCV_REGRESSION_THREAD_COUNT", 1)} ") + s" SEED=${testSeed} "
|
||||
val stdCmd = (s"make run REGRESSION_PATH=../../src/test/cpp/regression VEXRISCV_FILE=VexRiscv.v WITH_USER_IO=no REDO=10 TRACE=${if(debug) "yes" else "no"} TRACE_START=1000000000000l STOP_ON_ERROR=no FLOW_INFO=no STOP_ON_ERROR=no DHRYSTONE=yes COREMARK=${coremarkRegression} THREAD_COUNT=1 ") + s" SEED=${testSeed} "
|
||||
val testCmd = stdCmd + (positionsToApply).map(_.testParam).mkString(" ")
|
||||
println(testCmd)
|
||||
val str = doCmd(testCmd)
|
||||
assert(str.contains("REGRESSION SUCCESS") && !str.contains("Broken pipe"))
|
||||
val pattern = "Had simulate ([0-9]+)".r
|
||||
val hit = pattern.findFirstMatchIn(str)
|
||||
|
||||
lock.synchronized(clockCounter += hit.get.group(1).toLong)
|
||||
}
|
||||
}
|
||||
|
||||
var testId : Option[mutable.HashSet[Int]] = None
|
||||
var seed = sys.env.getOrElse("VEXRISCV_REGRESSION_SEED", Random.nextInt(1000000000).toString).toLong
|
||||
|
||||
// val testId = Some(mutable.HashSet(3,4,9,11,13,16,18,19,20,21))
|
||||
// val testId = Some(mutable.HashSet(15))
|
||||
// seed = -7374992264756372315l
|
||||
// testId = Some(mutable.HashSet(1,2,6,14,15,16,19))
|
||||
// testId = Some(mutable.HashSet(1,2,6,14))
|
||||
// testId = Some(mutable.HashSet(1))
|
||||
|
||||
|
||||
val rand = new Random(seed)
|
||||
|
||||
test("Info"){
|
||||
println(s"MAIN_SEED=$seed")
|
||||
}
|
||||
println(s"Seed=$seed")
|
||||
for(i <- 0 until sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_COUNT", "100").toInt){
|
||||
for(i <- 0 until testCount){
|
||||
var positions : List[VexRiscvPosition] = null
|
||||
var universe = mutable.HashSet[VexRiscvUniverse]()
|
||||
if(rand.nextDouble() < 0.5) universe += VexRiscvUniverse.EXECUTE_RF
|
||||
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_LINUX_RATE", "0.3").toDouble > rand.nextDouble()) {
|
||||
if(linuxRate > rand.nextDouble()) {
|
||||
universe += VexRiscvUniverse.CATCH_ALL
|
||||
universe += VexRiscvUniverse.MMU
|
||||
universe += VexRiscvUniverse.FORCE_MULDIV
|
||||
universe += VexRiscvUniverse.SUPERVISOR
|
||||
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_DEMW_RATE", "0.6").toDouble < rand.nextDouble()){
|
||||
if(demwRate < rand.nextDouble()){
|
||||
universe += VexRiscvUniverse.NO_WRITEBACK
|
||||
}
|
||||
} else {
|
||||
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE", "0.5").toDouble > rand.nextDouble()) {
|
||||
if(machineOsRate > rand.nextDouble()) {
|
||||
universe += VexRiscvUniverse.CATCH_ALL
|
||||
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_DEMW_RATE", "0.6").toDouble < rand.nextDouble()){
|
||||
if(demwRate < rand.nextDouble()){
|
||||
universe += VexRiscvUniverse.NO_WRITEBACK
|
||||
}
|
||||
}
|
||||
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_DEMW_RATE", "0.6").toDouble > rand.nextDouble()){
|
||||
}else if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_DEM_RATE", "0.5").toDouble > rand.nextDouble()){
|
||||
if(demwRate > rand.nextDouble()){
|
||||
}else if(demRate > rand.nextDouble()){
|
||||
universe += VexRiscvUniverse.NO_WRITEBACK
|
||||
} else {
|
||||
universe += VexRiscvUniverse.NO_WRITEBACK
|
||||
|
@ -678,8 +767,13 @@ class TestIndividualFeatures extends FunSuite {
|
|||
}while(!positions.forall(_.isCompatibleWith(positions)))
|
||||
|
||||
val testSeed = rand.nextInt()
|
||||
if(testId.isEmpty || testId.get.contains(i))
|
||||
doTest(positions," random_" + i + "_", testSeed, universe)
|
||||
if(testId.contains(i))
|
||||
doTest(positions,"test_id_" + i + "_", testSeed, universe)
|
||||
Hack.dCounter += 1
|
||||
}
|
||||
testSingleThread("report"){
|
||||
val time = (System.currentTimeMillis() - startAt)*1e-3
|
||||
val clockPerSecond = (clockCounter/time*1e-3).toLong
|
||||
println(s"Duration=${(time/60).toInt}mn clocks=${(clockCounter*1e-6).toLong}M clockPerSecond=${clockPerSecond}K")
|
||||
}
|
||||
}
|
Loading…
Reference in New Issue