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VexRiscv
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Merge pull request #34 from mithro/master 

More README fixes
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Dolu1990 2018-07-21 18:38:57 +02:00 committed by GitHub
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@ -308,11 +308,14 @@ To generate the Murax SoC Hardware :
# To generate the SoC without any content in the ram
sbt "run-main vexriscv.demo.Murax"
# To generate the SoC with a demo program in the SoC
# Will blink led and echo UART RX to UART TX (in the verilator sim, type some text and press enter to send UART frames to the Murax RX pin)
# To generate the SoC with a demo program already in ram
sbt "run-main vexriscv.demo.MuraxWithRamInit"
```
The demo program included by default with `MuraxWithRamInit` will blink the
LEDs and echo characters received on the UART back to the user. To see this
when running the Verilator sim, type some text and press enter.
Then go in src/test/cpp/murax and run the simulation with :
```sh