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VexRiscv
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Add exception catch to iBusSimplePLugin (pass)

This commit is contained in:
Dolu1990 2018-05-09 18:43:48 +02:00
parent acccbf40e2
commit 7b37669a0f
3 changed files with 21 additions and 4 deletions
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2
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
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@ -287,7 +287,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
} }
if(!earlyInjection) if(!earlyInjection)
assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(INSTRUCTION)(5) && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend") assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(INSTRUCTION)(5) && arbitration.isStuck),"DBusSimplePlugin doesn't allow writeback stage stall when read happend")
//formal //formal
insert(FORMAL_MEM_RDATA) := input(MEMORY_READ_DATA) insert(FORMAL_MEM_RDATA) := input(MEMORY_READ_DATA)

4
src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
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@ -13,8 +13,8 @@ class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConf
catchAccessFault = config.catchAccessFault, catchAccessFault = config.catchAccessFault,
resetVector = BigInt(0x80000000l), resetVector = BigInt(0x80000000l),
keepPcPlus4 = false, keepPcPlus4 = false,
decodePcGen = true, decodePcGen = false,
compressedGen = true, compressedGen = false,
cmdToRspStageCount = 1, cmdToRspStageCount = 1,
rspStageGen = false, rspStageGen = false,
injectorReadyCutGen = false, injectorReadyCutGen = false,

19
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
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@ -119,10 +119,16 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
catchAddressMisaligned = true, catchAddressMisaligned = true,
injectorStage = true){ injectorStage = true){
var iBus : IBusSimpleBus = null var iBus : IBusSimpleBus = null
var decodeExceptionPort : Flow[ExceptionCause] = null
override def setup(pipeline: VexRiscv): Unit = { override def setup(pipeline: VexRiscv): Unit = {
super.setup(pipeline) super.setup(pipeline)
iBus = master(IBusSimpleBus(interfaceKeepData)).setName("iBus") iBus = master(IBusSimpleBus(interfaceKeepData)).setName("iBus")
if(catchAccessFault) {
val exceptionService = pipeline.service(classOf[ExceptionService])
decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1)
}
} }
override def build(pipeline: VexRiscv): Unit = { override def build(pipeline: VexRiscv): Unit = {
@ -168,9 +174,20 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
fetchRsp.rsp.error.clearWhen(!rspBuffer.io.pop.valid) //Avoid interference with instruction injection from the debug plugin fetchRsp.rsp.error.clearWhen(!rspBuffer.io.pop.valid) //Avoid interference with instruction injection from the debug plugin
var issueDetected = False
val join = StreamJoin(Seq(inputPipeline.last, rspBuffer.io.pop), fetchRsp) val join = StreamJoin(Seq(inputPipeline.last, rspBuffer.io.pop), fetchRsp)
inputPipeline.last.ready setWhen(!inputPipeline.last.valid) inputPipeline.last.ready setWhen(!inputPipeline.last.valid)
output << (if(rspStageGen) join.m2sPipeWithFlush(flush) else join) outputBeforeStage << join.haltWhen(issueDetected)
if(catchAccessFault){
decodeExceptionPort.valid := False
decodeExceptionPort.code := 1
decodeExceptionPort.badAddr := join.pc
when(join.valid && join.rsp.error && !issueDetected){
issueDetected \= True
decodeExceptionPort.valid := iBusRsp.readyForError
}
}
} }
} }
} }