Add exception catch to iBusSimplePLugin (pass)

src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala

@@ -287,7 +287,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
       }
 
       if(!earlyInjection)
-        assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(INSTRUCTION)(5) && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend")
+        assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(INSTRUCTION)(5) && arbitration.isStuck),"DBusSimplePlugin doesn't allow writeback stage stall when read happend")
 
       //formal
       insert(FORMAL_MEM_RDATA) := input(MEMORY_READ_DATA)

src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala

@@ -13,8 +13,8 @@ class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConf
   catchAccessFault = config.catchAccessFault,
   resetVector = BigInt(0x80000000l),
   keepPcPlus4 = false,
-  decodePcGen = true,
-  compressedGen = true,
+  decodePcGen = false,
+  compressedGen = false,
   cmdToRspStageCount = 1,
   rspStageGen = false,
   injectorReadyCutGen = false,

src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala

@@ -119,10 +119,16 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
     catchAddressMisaligned = true,
     injectorStage = true){
   var iBus : IBusSimpleBus = null
+  var decodeExceptionPort : Flow[ExceptionCause] = null
 
   override def setup(pipeline: VexRiscv): Unit = {
     super.setup(pipeline)
     iBus = master(IBusSimpleBus(interfaceKeepData)).setName("iBus")
+
+    if(catchAccessFault) {
+      val exceptionService = pipeline.service(classOf[ExceptionService])
+      decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1)
+    }
   }
 
   override def build(pipeline: VexRiscv): Unit = {
@@ -168,9 +174,20 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
         fetchRsp.rsp.error.clearWhen(!rspBuffer.io.pop.valid) //Avoid interference with instruction injection from the debug plugin
 
 
+        var issueDetected = False
         val join = StreamJoin(Seq(inputPipeline.last, rspBuffer.io.pop), fetchRsp)
         inputPipeline.last.ready setWhen(!inputPipeline.last.valid)
-        output << (if(rspStageGen) join.m2sPipeWithFlush(flush) else join)
+        outputBeforeStage << join.haltWhen(issueDetected)
+
+        if(catchAccessFault){
+          decodeExceptionPort.valid := False
+          decodeExceptionPort.code  := 1
+          decodeExceptionPort.badAddr := join.pc
+          when(join.valid && join.rsp.error && !issueDetected){
+            issueDetected \= True
+            decodeExceptionPort.valid  := iBusRsp.readyForError
+          }
+        }
       }
     }
   }