Remove PMP from MachineOs test defaults
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parent
f2ce2eab00
commit
7d699dcc13
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@ -5,7 +5,7 @@ import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
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import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
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import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
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import spinal.core._
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import spinal.core._
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object GenZephyr extends App {
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object GenSecure extends App {
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def cpu() = new VexRiscv(
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def cpu() = new VexRiscv(
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config = VexRiscvConfig(
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config = VexRiscvConfig(
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plugins = List(
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plugins = List(
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@ -71,7 +71,7 @@ object GenZephyr extends App {
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mulUnrollFactor = 1,
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mulUnrollFactor = 1,
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divUnrollFactor = 1
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divUnrollFactor = 1
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),
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),
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new CsrPlugin(CsrPluginConfig.zephyr(0x00000020l)),
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new CsrPlugin(CsrPluginConfig.secure(0x00000020l)),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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new BranchPlugin(
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earlyBranch = false,
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earlyBranch = false,
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@ -264,13 +264,13 @@ object CsrPluginConfig{
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uinstretAccess = CsrAccess.NONE
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uinstretAccess = CsrAccess.NONE
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)
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)
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def zephyr(mtvecInit : BigInt) = CsrPluginConfig(
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def secure(mtvecInit : BigInt) = CsrPluginConfig(
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catchIllegalAccess = true,
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catchIllegalAccess = true,
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mvendorid = 1,
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mvendorid = 1,
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marchid = 2,
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marchid = 2,
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mimpid = 3,
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mimpid = 3,
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mhartid = 0,
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mhartid = 0,
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misaExtensionsInit = 0x103124, // RV32CFIMNU
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misaExtensionsInit = 0x101064, // RV32GCFMU
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misaAccess = CsrAccess.READ_WRITE,
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misaAccess = CsrAccess.READ_WRITE,
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mtvecAccess = CsrAccess.READ_WRITE,
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mtvecAccess = CsrAccess.READ_WRITE,
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mtvecInit = mtvecInit,
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mtvecInit = mtvecInit,
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@ -1,3 +0,0 @@
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target remote localhost:3333
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monitor reset halt
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load
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@ -517,6 +517,7 @@ trait CatchAllPosition
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class CsrDimension(freertos : String, zephyr : String, linux : String) extends VexRiscvDimension("Csr") {
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class CsrDimension(freertos : String, zephyr : String, linux : String) extends VexRiscvDimension("Csr") {
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override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
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override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
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val pmp = universes.contains(VexRiscvUniverse.PMP)
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val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
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val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
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val supervisor = universes.contains(VexRiscvUniverse.SUPERVISOR)
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val supervisor = universes.contains(VexRiscvUniverse.SUPERVISOR)
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if(supervisor){
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if(supervisor){
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@ -524,9 +525,14 @@ class CsrDimension(freertos : String, zephyr : String, linux : String) extends V
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.linuxFull(0x80000020l))
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.linuxFull(0x80000020l))
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override def testParam = s"FREERTOS=$freertos ZEPHYR=$zephyr LINUX_REGRESSION=$linux SUPERVISOR=yes"
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override def testParam = s"FREERTOS=$freertos ZEPHYR=$zephyr LINUX_REGRESSION=$linux SUPERVISOR=yes"
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}
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}
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} else if(pmp){
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new VexRiscvPosition("Secure") with CatchAllPosition{
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.secure(0x80000020l))
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override def testParam = s"CSR=yes CSR_SKIP_TEST=yes FREERTOS=$freertos ZEPHYR=$zephyr"
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}
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} else if(catchAll){
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} else if(catchAll){
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new VexRiscvPosition("MachineOs") with CatchAllPosition{
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new VexRiscvPosition("MachineOs") with CatchAllPosition{
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.zephyr(0x80000020l))
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.all(0x80000020l))
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override def testParam = s"CSR=yes CSR_SKIP_TEST=yes FREERTOS=$freertos ZEPHYR=$zephyr"
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override def testParam = s"CSR=yes CSR_SKIP_TEST=yes FREERTOS=$freertos ZEPHYR=$zephyr"
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}
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}
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} else if(r.nextDouble() < 0.3){
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} else if(r.nextDouble() < 0.3){
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@ -655,6 +661,7 @@ class TestIndividualFeatures extends MultithreadedFunSuite {
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val rvcRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_RVC_RATE", "0.5").toDouble
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val rvcRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_RVC_RATE", "0.5").toDouble
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val linuxRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_LINUX_RATE", "0.3").toDouble
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val linuxRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_LINUX_RATE", "0.3").toDouble
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val machineOsRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE", "0.5").toDouble
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val machineOsRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE", "0.5").toDouble
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val secureRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_SECURE_RATE", "0.5").toDouble
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val linuxRegression = sys.env.getOrElse("VEXRISCV_REGRESSION_LINUX_REGRESSION", "yes")
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val linuxRegression = sys.env.getOrElse("VEXRISCV_REGRESSION_LINUX_REGRESSION", "yes")
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val coremarkRegression = sys.env.getOrElse("VEXRISCV_REGRESSION_COREMARK", "yes")
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val coremarkRegression = sys.env.getOrElse("VEXRISCV_REGRESSION_COREMARK", "yes")
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val zephyrCount = sys.env.getOrElse("VEXRISCV_REGRESSION_ZEPHYR_COUNT", "4")
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val zephyrCount = sys.env.getOrElse("VEXRISCV_REGRESSION_ZEPHYR_COUNT", "4")
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@ -761,17 +768,26 @@ class TestIndividualFeatures extends MultithreadedFunSuite {
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if(demwRate < rand.nextDouble()){
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if(demwRate < rand.nextDouble()){
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universe += VexRiscvUniverse.NO_WRITEBACK
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universe += VexRiscvUniverse.NO_WRITEBACK
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}
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}
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} else {
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} else if (secureRate > rand.nextDouble()) {
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if(machineOsRate > rand.nextDouble()) {
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universe += VexRiscvUniverse.CACHE_ALL
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universe += VexRiscvUniverse.CACHE_ALL
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universe += VexRiscvUniverse.CATCH_ALL
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universe += VexRiscvUniverse.CATCH_ALL
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universe += VexRiscvUniverse.PMP
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universe += VexRiscvUniverse.PMP
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if(demwRate < rand.nextDouble()){
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if(demwRate < rand.nextDouble()){
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universe += VexRiscvUniverse.NO_WRITEBACK
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universe += VexRiscvUniverse.NO_WRITEBACK
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}
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}
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} else {
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if(machineOsRate > rand.nextDouble()) {
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universe += VexRiscvUniverse.CATCH_ALL
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if(demwRate < rand.nextDouble()){
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universe += VexRiscvUniverse.NO_WRITEBACK
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}
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}
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}
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if(demRate > rand.nextDouble()){
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if(demwRate > rand.nextDouble()){
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}else if(demRate > rand.nextDouble()){
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universe += VexRiscvUniverse.NO_WRITEBACK
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universe += VexRiscvUniverse.NO_WRITEBACK
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} else {
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universe += VexRiscvUniverse.NO_WRITEBACK
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universe += VexRiscvUniverse.NO_MEMORY
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}
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}
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}
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}
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