Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Remove PMP from MachineOs test defaults

This commit is contained in:
Samuel Lindemer 2020-12-10 09:39:56 +01:00
parent f2ce2eab00
commit 7d699dcc13
5 changed files with 25 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/vexriscv/demo/GenZephyr.scala → src/main/scala/vexriscv/demo/GenSecure.scala
View File

@ -5,7 +5,7 @@ import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
import spinal.core._
object GenZephyr extends App {
object GenSecure extends App {
def cpu() = new VexRiscv(
config = VexRiscvConfig(
plugins = List(
@ -71,7 +71,7 @@ object GenZephyr extends App {
mulUnrollFactor = 1,
divUnrollFactor = 1
),
new CsrPlugin(CsrPluginConfig.zephyr(0x00000020l)),
new CsrPlugin(CsrPluginConfig.secure(0x00000020l)),
new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
new BranchPlugin(
earlyBranch = false,

4
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -264,13 +264,13 @@ object CsrPluginConfig{
uinstretAccess = CsrAccess.NONE
)
def zephyr(mtvecInit : BigInt) = CsrPluginConfig(
def secure(mtvecInit : BigInt) = CsrPluginConfig(
catchIllegalAccess = true,
mvendorid = 1,
marchid = 2,
mimpid = 3,
mhartid = 0,
misaExtensionsInit = 0x103124, // RV32CFIMNU
misaExtensionsInit = 0x101064, // RV32GCFMU
misaAccess = CsrAccess.READ_WRITE,
mtvecAccess = CsrAccess.READ_WRITE,
mtvecInit = mtvecInit,

3
src/test/cpp/raw/pmp/.gdbinit
View File

@ -1,3 +0,0 @@
target remote localhost:3333
monitor reset halt
load

24
src/test/scala/vexriscv/TestIndividualFeatures.scala
View File

@ -517,6 +517,7 @@ trait CatchAllPosition
class CsrDimension(freertos : String, zephyr : String, linux : String) extends VexRiscvDimension("Csr") {
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
val pmp = universes.contains(VexRiscvUniverse.PMP)
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
val supervisor = universes.contains(VexRiscvUniverse.SUPERVISOR)
if(supervisor){
@ -524,9 +525,14 @@ class CsrDimension(freertos : String, zephyr : String, linux : String) extends V
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.linuxFull(0x80000020l))
override def testParam = s"FREERTOS=$freertos ZEPHYR=$zephyr LINUX_REGRESSION=$linux SUPERVISOR=yes"
}
} else if(pmp){
new VexRiscvPosition("Secure") with CatchAllPosition{
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.secure(0x80000020l))
override def testParam = s"CSR=yes CSR_SKIP_TEST=yes FREERTOS=$freertos ZEPHYR=$zephyr"
}
} else if(catchAll){
new VexRiscvPosition("MachineOs") with CatchAllPosition{
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.zephyr(0x80000020l))
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.all(0x80000020l))
override def testParam = s"CSR=yes CSR_SKIP_TEST=yes FREERTOS=$freertos ZEPHYR=$zephyr"
}
} else if(r.nextDouble() < 0.3){
@ -655,6 +661,7 @@ class TestIndividualFeatures extends MultithreadedFunSuite {
val rvcRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_RVC_RATE", "0.5").toDouble
val linuxRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_LINUX_RATE", "0.3").toDouble
val machineOsRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE", "0.5").toDouble
val secureRate = sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_SECURE_RATE", "0.5").toDouble
val linuxRegression = sys.env.getOrElse("VEXRISCV_REGRESSION_LINUX_REGRESSION", "yes")
val coremarkRegression = sys.env.getOrElse("VEXRISCV_REGRESSION_COREMARK", "yes")
val zephyrCount = sys.env.getOrElse("VEXRISCV_REGRESSION_ZEPHYR_COUNT", "4")
@ -761,17 +768,26 @@ class TestIndividualFeatures extends MultithreadedFunSuite {
if(demwRate < rand.nextDouble()){
universe += VexRiscvUniverse.NO_WRITEBACK
}
} else {
if(machineOsRate > rand.nextDouble()) {
} else if (secureRate > rand.nextDouble()) {
universe += VexRiscvUniverse.CACHE_ALL
universe += VexRiscvUniverse.CATCH_ALL
universe += VexRiscvUniverse.PMP
if(demwRate < rand.nextDouble()){
universe += VexRiscvUniverse.NO_WRITEBACK
}
} else {
if(machineOsRate > rand.nextDouble()) {
universe += VexRiscvUniverse.CATCH_ALL
if(demwRate < rand.nextDouble()){
universe += VexRiscvUniverse.NO_WRITEBACK
}
}
if(demRate > rand.nextDouble()){
if(demwRate > rand.nextDouble()){
}else if(demRate > rand.nextDouble()){
universe += VexRiscvUniverse.NO_WRITEBACK
} else {
universe += VexRiscvUniverse.NO_WRITEBACK
universe += VexRiscvUniverse.NO_MEMORY
}
}