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VexRiscvSmpCluster now avoid useless decoder for plic/clint

This commit is contained in:
Dolu1990 2020-08-13 11:26:11 +02:00
parent 69d5ba239a
commit 7dcaa0c390
1 changed files with 37 additions and 10 deletions
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47
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -82,21 +82,48 @@ class VexRiscvSmpClusterWithPeripherals(p : VexRiscvSmpClusterParameter) extends
val peripheral = peripheralBridge.produceIo(peripheralBridge.logic.io.output) val peripheral = peripheralBridge.produceIo(peripheralBridge.logic.io.output)
interconnect.slaves(peripheralBridge.bmb).forceAccessSourceDataWidth(32) interconnect.slaves(peripheralBridge.bmb).forceAccessSourceDataWidth(32)
val plic = BmbPlicGenerator(0) val plic = BmbPlicGenerator()(interconnect = null)
plic.priorityWidth.load(2) plic.priorityWidth.load(2)
plic.mapping.load(PlicMapping.sifive) plic.mapping.load(PlicMapping.sifive)
val plicWishboneBridge = WishboneToBmbGenerator() val plicWishboneBridge = new Generator{
val plicWishbone = plicWishboneBridge.produceIo(plicWishboneBridge.logic.io.input) dependencies += plic.ctrl
plicWishboneBridge.config.load(WishboneConfig(20, 32))
interconnect.addConnection(plicWishboneBridge.bmb, plic.ctrl)
val clint = BmbClintGenerator(0) plic.accessRequirements.load(BmbAccessParameter(
addressWidth = 22,
dataWidth = 32
).addSources(1, BmbSourceParameter(
contextWidth = 0,
lengthWidth = 2,
alignment = BmbParameter.BurstAlignement.LENGTH
)))
val clintWishboneBridge = WishboneToBmbGenerator() val logic = add task new Area{
val clintWishbone = clintWishboneBridge.produceIo(clintWishboneBridge.logic.io.input) val bridge = WishboneToBmb(WishboneConfig(20, 32))
clintWishboneBridge.config.load(WishboneConfig(14, 32)) bridge.io.output >> plic.ctrl
interconnect.addConnection(clintWishboneBridge.bmb, clint.ctrl) }
}
val plicWishbone = plicWishboneBridge.produceIo(plicWishboneBridge.logic.bridge.io.input)
val clint = BmbClintGenerator(0)(interconnect = null)
val clintWishboneBridge = new Generator{
dependencies += clint.ctrl
clint.accessRequirements.load(BmbAccessParameter(
addressWidth = 16,
dataWidth = 32
).addSources(1, BmbSourceParameter(
contextWidth = 0,
lengthWidth = 2,
alignment = BmbParameter.BurstAlignement.LENGTH
)))
val logic = add task new Area{
val bridge = WishboneToBmb(WishboneConfig(14, 32))
bridge.io.output >> clint.ctrl
}
}
val clintWishbone = clintWishboneBridge.produceIo(clintWishboneBridge.logic.bridge.io.input)
val interrupts = add task (in Bits(32 bits)) val interrupts = add task (in Bits(32 bits))
for(i <- 1 to 31) yield plic.addInterrupt(interrupts.derivate(_.apply(i)), i) for(i <- 1 to 31) yield plic.addInterrupt(interrupts.derivate(_.apply(i)), i)